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llvm14
riscv-generic.patch
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File riscv-generic.patch of Package llvm14
From edd6632127975c61181dc8003c1271d4d86255b1 Mon Sep 17 00:00:00 2001 From: Craig Topper <craig.topper@sifive.com> Date: Wed, 9 Mar 2022 16:43:17 -0800 Subject: [PATCH] [RISCV] Support 'generic' as a valid CPU name. Most other targets support 'generic', but RISCV issues an error. This can require a special case in tools that use LLVM that aren't clang. This patch treats "generic" the same as an empty string and remaps it to generic-rv/rv64 based on the triple. Unfortunately, it has to be added to RISCV.td because MCSubtargetInfo is constructed and parses the CPU before RISCVSubtarget's constructor gets a chance to remap it. The CPU will then reparsed and the state in the MCSubtargetInfo subclass will be updated again. Fixes PR54146. Reviewed By: khchen Differential Revision: https://reviews.llvm.org/D121149 --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 5 +---- llvm/lib/Target/RISCV/RISCV.td | 3 +++ llvm/lib/Target/RISCV/RISCVSubtarget.cpp | 5 +---- 3 files changed, 5 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp index 07c2be624932..1580c55947ff 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp @@ -77,11 +77,8 @@ createRISCVMCObjectFileInfo(MCContext &Ctx, bool PIC, static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { - if (CPU.empty()) + if (CPU.empty() || CPU == "generic") CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32"; - if (CPU == "generic") - report_fatal_error(Twine("CPU 'generic' is not supported. Use ") + - (TT.isArch64Bit() ? "generic-rv64" : "generic-rv32")); return createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); } diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index adf20c821066..952e01d886f9 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -452,6 +452,9 @@ include "RISCVSchedSiFive7.td" def : ProcessorModel<"generic-rv32", NoSchedModel, []>; def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>; +// Support generic for compatibility with other targets. The triple will be used +// to change to the appropriate rv32/rv64 version. +def : ProcessorModel<"generic", NoSchedModel, []>; def : ProcessorModel<"rocket-rv32", RocketModel, []>; def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>; diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp index 976e4ccb1422..3aa69e851df3 100644 --- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp @@ -69,11 +69,8 @@ RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU, StringRef ABIName) { // Determine default and user-specified characteristics bool Is64Bit = TT.isArch64Bit(); - if (CPU.empty()) + if (CPU.empty() || CPU == "generic") CPU = Is64Bit ? "generic-rv64" : "generic-rv32"; - if (CPU == "generic") - report_fatal_error(Twine("CPU 'generic' is not supported. Use ") + - (Is64Bit ? "generic-rv64" : "generic-rv32")); if (TuneCPU.empty()) TuneCPU = CPU; -- 2.41.0
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