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File libpfm_enable-ibm-power9-core-pmu-support-beta.patch of Package libpfm (Revision 4bc59235482d9c14451d644efdd161fd)

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From: Will Schmidt <will_schmidt@vnet.ibm.com>
Date: Fri, 21 Apr 2017 17:25:45 -0700
Subject: Enable IBM Power9 core PMU support (beta)
Git-repo: git://git.code.sf.net/p/perfmon2/libpfm4
Git-commit: ae1a66c16313ea1d96d99a293c2b7dab095b9880
References: FATE#322254
Signed-off-by: Tony Jones <tonyj@suse.de>

[suse: adjust for context; no 321133e1 create internal type for perf_event_attr_info_t]

This patch is build tested only, thus the [RFC] tag. :-)
The event list itself is untested and thus subject to change.

Add POWER9 support.

diff --git a/README b/README
index 6a49591..92d9950 100644
--- a/README
+++ b/README
@@ -79,6 +79,7 @@ The library supports many PMUs. The current version can handle:
 		Power 7
 		Power 8
 		Power 8 Nest
+		Power 9
 		PPC970
 		Torrent
 		System z (s390x)
diff --git a/include/perfmon/pfmlib.h b/include/perfmon/pfmlib.h
index 6904c1c..89ab973 100644
--- a/include/perfmon/pfmlib.h
+++ b/include/perfmon/pfmlib.h
@@ -367,6 +367,8 @@ typedef enum {
 
 	PFM_PMU_INTEL_KNL_UNC_UBOX,	/* Intel KnightLanding Ubox uncore */
 	PFM_PMU_INTEL_KNL_UNC_M2PCIE,	/* Intel KnightLanding M2PCIe uncore */
+
+	PFM_PMU_POWER9,			/* IBM POWER9 */
 	/* MUST ADD NEW PMU MODELS HERE */
 
 	PFM_PMU_MAX			/* end marker */
diff --git a/lib/Makefile b/lib/Makefile
index 72f26d7..f532561 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -124,7 +124,7 @@ SRCS += pfmlib_powerpc_perf_event.c
 endif
 
 INCARCH = $(INC_POWERPC)
-SRCS   += pfmlib_powerpc.c pfmlib_power4.c pfmlib_ppc970.c pfmlib_power5.c pfmlib_power6.c pfmlib_power7.c pfmlib_torrent.c pfmlib_power8.c pfmlib_powerpc_nest.c
+SRCS   += pfmlib_powerpc.c pfmlib_power4.c pfmlib_ppc970.c pfmlib_power5.c pfmlib_power6.c pfmlib_power7.c pfmlib_torrent.c pfmlib_power8.c pfmlib_power9.c pfmlib_powerpc_nest.c
 CFLAGS += -DCONFIG_PFMLIB_ARCH_POWERPC
 endif
 
@@ -291,6 +291,7 @@ INC_POWERPC=events/ppc970_events.h	\
 	events/power6_events.h		\
 	events/power7_events.h		\
 	events/power8_events.h		\
+	events/power9_events.h		\
 	events/torrent_events.h		\
 	events/powerpc_nest_events.h
 
diff --git a/lib/events/power9_events.h b/lib/events/power9_events.h
new file mode 100644
index 0000000..7414687
--- /dev/null
+++ b/lib/events/power9_events.h
@@ -0,0 +1,6460 @@
+/*
+* File:    power9_events.h
+* CVS:
+* Author:  Will Schmidt
+*          will_schmidt@vnet.ibm.com
+* Author:  Carl Love
+*          cel@us.ibm.com
+*
+* Mods:
+* Initial content generated by Will Schmidt.  (Jan 31, 2017).
+*
+* Contributed by
+* (C) Copyright IBM Corporation, 2017.  All Rights Reserved.
+*
+* Note: This code was automatically generated and should not be modified by
+* hand.
+*
+* Documentation on the PMU events will be published at:
+*  ...
+*/
+
+#ifndef __POWER9_EVENTS_H__
+#define __POWER8_EVENTS_H__
+
+#define POWER9_PME_PM_IERAT_RELOAD 0
+#define POWER9_PME_PM_TM_OUTER_TEND 1
+#define POWER9_PME_PM_IPTEG_FROM_L3 2
+#define POWER9_PME_PM_DPTEG_FROM_L3_1_MOD 3
+#define POWER9_PME_PM_PMC2_SAVED 4
+#define POWER9_PME_PM_LSU_FLUSH_SAO 5
+#define POWER9_PME_PM_CMPLU_STALL_DFU 6
+#define POWER9_PME_PM_MRK_LSU_FLUSH_RELAUNCH_MISS 7
+#define POWER9_PME_PM_SP_FLOP_CMPL 8
+#define POWER9_PME_PM_IC_RELOAD_PRIVATE 9
+#define POWER9_PME_PM_RADIX_PWC_L2_PTE_FROM_L2 10
+#define POWER9_PME_PM_INST_PUMP_CPRED 11
+#define POWER9_PME_PM_INST_FROM_L2_1_MOD 12
+#define POWER9_PME_PM_MRK_ST_CMPL 13
+#define POWER9_PME_PM_MRK_LSU_DERAT_MISS 14
+#define POWER9_PME_PM_L2_ST_DISP 15
+#define POWER9_PME_PM_LSU0_FALSE_LHS 16
+#define POWER9_PME_PM_L2_CASTOUT_MOD 17
+#define POWER9_PME_PM_L2_RCST_DISP_FAIL_ADDR 18
+#define POWER9_PME_PM_MRK_INST_TIMEO 19
+#define POWER9_PME_PM_CMPLU_STALL_LOAD_FINISH 20
+#define POWER9_PME_PM_INST_FROM_L2_1_SHR 21
+#define POWER9_PME_PM_LS1_DC_COLLISIONS 22
+#define POWER9_PME_PM_LSU2_FALSE_LHS 23
+#define POWER9_PME_PM_MRK_ST_DRAIN_TO_L2DISP_CYC 24
+#define POWER9_PME_PM_MRK_DTLB_MISS_16M 25
+#define POWER9_PME_PM_L2_GROUP_PUMP 26
+#define POWER9_PME_PM_LSU2_VECTOR_ST_FIN 27
+#define POWER9_PME_PM_CMPLU_STALL_LSAQ_ARB 28
+#define POWER9_PME_PM_L3_CO_LCO 29
+#define POWER9_PME_PM_INST_GRP_PUMP_CPRED 30
+#define POWER9_PME_PM_THRD_PRIO_4_5_CYC 31
+#define POWER9_PME_PM_BR_PRED_TA 32
+#define POWER9_PME_PM_ICT_NOSLOT_BR_MPRED_ICMISS 33
+#define POWER9_PME_PM_IPTEG_FROM_L3_NO_CONFLICT 34
+#define POWER9_PME_PM_CMPLU_STALL_FXU 35
+#define POWER9_PME_PM_VSU_FSQRT_FDIV 36
+#define POWER9_PME_PM_EXT_INT 37
+#define POWER9_PME_PM_MRK_LD_MISS_EXPOSED_CYC 38
+#define POWER9_PME_PM_S2Q_FULL 39
+#define POWER9_PME_PM_RUN_CYC_SMT2_MODE 40
+#define POWER9_PME_PM_DECODE_LANES_NOT_AVAIL 41
+#define POWER9_PME_PM_TM_FAIL_TLBIE 42
+#define POWER9_PME_PM_DISP_CLB_HELD_BAL 43
+#define POWER9_PME_PM_MRK_DATA_FROM_L3MISS_CYC 44
+#define POWER9_PME_PM_MRK_ST_FWD 45
+#define POWER9_PME_PM_FXU_FIN 46
+#define POWER9_PME_PM_SYNC_MRK_BR_MPRED 47
+#define POWER9_PME_PM_CMPLU_STALL_STORE_FIN_ARB 48
+#define POWER9_PME_PM_DSLB_MISS 49
+#define POWER9_PME_PM_L3_MISS 50
+#define POWER9_PME_PM_DUMMY2_REMOVE_ME 51
+#define POWER9_PME_PM_MRK_DERAT_MISS_1G 52
+#define POWER9_PME_PM_MATH_FLOP_CMPL 53
+#define POWER9_PME_PM_L2_INST 54
+#define POWER9_PME_PM_FLUSH_DISP 55
+#define POWER9_PME_PM_DISP_HELD_ISSQ_FULL 56
+#define POWER9_PME_PM_MEM_READ 57
+#define POWER9_PME_PM_DATA_PUMP_MPRED 58
+#define POWER9_PME_PM_DATA_CHIP_PUMP_CPRED 59
+#define POWER9_PME_PM_MRK_DATA_FROM_DMEM 60
+#define POWER9_PME_PM_CMPLU_STALL_LSU 61
+#define POWER9_PME_PM_DATA_FROM_L3_1_MOD 62
+#define POWER9_PME_PM_MRK_DERAT_MISS_16M 63
+#define POWER9_PME_PM_TM_TRANS_RUN_CYC 64
+#define POWER9_PME_PM_THRD_ALL_RUN_CYC 65
+#define POWER9_PME_PM_DATA_FROM_DL2L3_MOD 66
+#define POWER9_PME_PM_MRK_BR_MPRED_CMPL 67
+#define POWER9_PME_PM_ICT_NOSLOT_DISP_HELD_ISSQ 68
+#define POWER9_PME_PM_MRK_INST 69
+#define POWER9_PME_PM_TABLEWALK_CYC_PREF 70
+#define POWER9_PME_PM_LSU1_ERAT_HIT 71
+#define POWER9_PME_PM_NTC_ISSUE_HELD_OTHER 72
+#define POWER9_PME_PM_CMPLU_STALL_LSU_FLUSH_NEXT 73
+#define POWER9_PME_PM_MRK_DPTEG_FROM_L2 74
+#define POWER9_PME_PM_LS1_TM_DISALLOW 75
+#define POWER9_PME_PM_INST_FROM_L2_DISP_CONFLICT_LDHITST 76
+#define POWER9_PME_PM_BR_PRED_PCACHE 77
+#define POWER9_PME_PM_MRK_BACK_BR_CMPL 78
+#define POWER9_PME_PM_RD_CLEARING_SC 79
+#define POWER9_PME_PM_PMC1_OVERFLOW 80
+#define POWER9_PME_PM_L2_RTY_ST 81
+#define POWER9_PME_PM_IPTEG_FROM_L2_NO_CONFLICT 82
+#define POWER9_PME_PM_LSU1_FALSE_LHS 83
+#define POWER9_PME_PM_LSU0_VECTOR_ST_FIN 84
+#define POWER9_PME_PM_MEM_LOC_THRESH_LSU_HIGH 85
+#define POWER9_PME_PM_LS2_UNALIGNED_LD 86
+#define POWER9_PME_PM_BR_TAKEN_CMPL 87
+#define POWER9_PME_PM_DATA_SYS_PUMP_MPRED 88
+#define POWER9_PME_PM_ISQ_36_44_ENTRIES 89
+#define POWER9_PME_PM_LSU1_VECTOR_LD_FIN 90
+#define POWER9_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER 91
+#define POWER9_PME_PM_ICT_NOSLOT_IC_MISS 92
+#define POWER9_PME_PM_LSU3_TM_L1_HIT 93
+#define POWER9_PME_PM_MRK_INST_DISP 94
+#define POWER9_PME_PM_VECTOR_FLOP_CMPL 95
+#define POWER9_PME_PM_FXU_IDLE 96
+#define POWER9_PME_PM_INST_CMPL 97
+#define POWER9_PME_PM_EAT_FORCE_MISPRED 98
+#define POWER9_PME_PM_CMPLU_STALL_LRQ_FULL 99
+#define POWER9_PME_PM_MRK_DATA_FROM_DL2L3_MOD 100
+#define POWER9_PME_PM_BACK_BR_CMPL 101
+#define POWER9_PME_PM_NEST_REF_CLK 102
+#define POWER9_PME_PM_MRK_DPTEG_FROM_RL2L3_SHR 103
+#define POWER9_PME_PM_RC_USAGE 104
+#define POWER9_PME_PM_MRK_DPTEG_FROM_L3_1_ECO_MOD 105
+#define POWER9_PME_PM_BR_CMPL 106
+#define POWER9_PME_PM_INST_FROM_RL2L3_MOD 107
+#define POWER9_PME_PM_SHL_CREATED 108
+#define POWER9_PME_PM_CMPLU_STALL_PASTE 109
+#define POWER9_PME_PM_LSU3_LDMX_FIN 110
+#define POWER9_PME_PM_SN_USAGE 111
+#define POWER9_PME_PM_L2_ST_HIT 112
+#define POWER9_PME_PM_DATA_FROM_DMEM 113
+#define POWER9_PME_PM_CMPLU_STALL_DMISS_REMOTE 114
+#define POWER9_PME_PM_LSU2_LDMX_FIN 115
+#define POWER9_PME_PM_L3_LD_MISS 116
+#define POWER9_PME_PM_DPTEG_FROM_RL4 117
+#define POWER9_PME_PM_RADIX_PWC_L3_PDE_FROM_L2 118
+#define POWER9_PME_PM_MRK_DATA_FROM_RL4_CYC 119
+#define POWER9_PME_PM_TM_SC_CO 120
+#define POWER9_PME_PM_L2_SN_SX_I_DONE 121
+#define POWER9_PME_PM_DPTEG_FROM_L3_DISP_CONFLICT 122
+#define POWER9_PME_PM_ISIDE_L2MEMACC 123
+#define POWER9_PME_PM_L3_P0_GRP_PUMP 124
+#define POWER9_PME_PM_IPTEG_FROM_DL2L3_SHR 125
+#define POWER9_PME_PM_RADIX_PWC_L3_PDE_FROM_L3 126
+#define POWER9_PME_PM_THRESH_MET 127
+#define POWER9_PME_PM_DATA_FROM_L2_MEPF 128
+#define POWER9_PME_PM_DISP_STARVED 129
+#define POWER9_PME_PM_L3_P0_LCO_RTY 130
+#define POWER9_PME_PM_NTC_ISSUE_HELD_DARQ_FULL 131
+#define POWER9_PME_PM_L3_RD_USAGE 132
+#define POWER9_PME_PM_TLBIE_FIN 133
+#define POWER9_PME_PM_DPTEG_FROM_LL4 134
+#define POWER9_PME_PM_CMPLU_STALL_TLBIE 135
+#define POWER9_PME_PM_MRK_DATA_FROM_L2MISS_CYC 136
+#define POWER9_PME_PM_LS3_DC_COLLISIONS 137
+#define POWER9_PME_PM_L1_ICACHE_MISS 138
+#define POWER9_PME_PM_LSU_REJECT_ERAT_MISS 139
+#define POWER9_PME_PM_DATA_SYS_PUMP_CPRED 140
+#define POWER9_PME_PM_MRK_FAB_RSP_RWITM_CYC 141
+#define POWER9_PME_PM_MRK_DATA_FROM_L3_1_SHR_CYC 142
+#define POWER9_PME_PM_LSU_FLUSH_UE 143
+#define POWER9_PME_PM_BR_PRED_TAKEN_CR 144
+#define POWER9_PME_PM_INST_FROM_L2_DISP_CONFLICT_OTHER 145
+#define POWER9_PME_PM_MRK_DPTEG_FROM_DL2L3_SHR 146
+#define POWER9_PME_PM_DATA_FROM_L2_1_MOD 147
+#define POWER9_PME_PM_LSU_FLUSH_LHL_SHL 148
+#define POWER9_PME_PM_L3_P1_PF_RTY 149
+#define POWER9_PME_PM_MRK_DPTEG_FROM_DL2L3_MOD 150
+#define POWER9_PME_PM_DFU_BUSY 151
+#define POWER9_PME_PM_LSU1_TM_L1_MISS 152
+#define POWER9_PME_PM_FREQ_UP 153
+#define POWER9_PME_PM_DATA_FROM_LMEM 154
+#define POWER9_PME_PM_MRK_DATA_FROM_L2_MEPF 155
+#define POWER9_PME_PM_ISIDE_DISP 156
+#define POWER9_PME_PM_TM_OUTER_TBEGIN 157
+#define POWER9_PME_PM_PMC3_OVERFLOW 158
+#define POWER9_PME_PM_LSU0_SET_MPRED 159
+#define POWER9_PME_PM_INST_FROM_L2_MEPF 160
+#define POWER9_PME_PM_L3_P0_NODE_PUMP 161
+#define POWER9_PME_PM_IPTEG_FROM_L3_1_MOD 162
+#define POWER9_PME_PM_L3_PF_USAGE 163
+#define POWER9_PME_PM_CMPLU_STALL_BRU 164
+#define POWER9_PME_PM_ISLB_MISS 165
+#define POWER9_PME_PM_CYC 166
+#define POWER9_PME_PM_MRK_DATA_FROM_L3_1_SHR 167
+#define POWER9_PME_PM_IPTEG_FROM_RL2L3_MOD 168
+#define POWER9_PME_PM_DARQ_10_12_ENTRIES 169
+#define POWER9_PME_PM_LSU2_3_LRQF_FULL_CYC 170
+#define POWER9_PME_PM_DECODE_FUSION_OP_PRESERV 171
+#define POWER9_PME_PM_MRK_DPTEG_FROM_L2_MEPF 172
+#define POWER9_PME_PM_MRK_L1_RELOAD_VALID 173
+#define POWER9_PME_PM_LSU2_SET_MPRED 174
+#define POWER9_PME_PM_1PLUS_PPC_CMPL 175
+#define POWER9_PME_PM_DATA_FROM_LL4 176
+#define POWER9_PME_PM_CMPLU_STALL_DMISS_L3MISS 177
+#define POWER9_PME_PM_TM_CAP_OVERFLOW 178
+#define POWER9_PME_PM_MRK_DPTEG_FROM_LMEM 179
+#define POWER9_PME_PM_LSU3_FALSE_LHS 180
+#define POWER9_PME_PM_THRESH_EXC_512 181
+#define POWER9_PME_PM_RADIX_PWC_L1_PDE_FROM_L2 182
+#define POWER9_PME_PM_HWSYNC 183
+#define POWER9_PME_PM_TM_FAIL_FOOTPRINT_OVERFLOW 184
+#define POWER9_PME_PM_INST_SYS_PUMP_MPRED_RTY 185
+#define POWER9_PME_PM_ICT_NOSLOT_DISP_HELD_HB_FULL 186
+#define POWER9_PME_PM_DC_DEALLOC_NO_CONF 187
+#define POWER9_PME_PM_CMPLU_STALL_VFXLONG 188
+#define POWER9_PME_PM_MEM_LOC_THRESH_IFU 189
+#define POWER9_PME_PM_MRK_DATA_FROM_L3_CYC 190
+#define POWER9_PME_PM_PTE_PREFETCH 191
+#define POWER9_PME_PM_CMPLU_STALL_STORE_PIPE_ARB 192
+#define POWER9_PME_PM_CMPLU_STALL_SLB 193
+#define POWER9_PME_PM_MRK_DERAT_MISS_4K 194
+#define POWER9_PME_PM_CMPLU_STALL_LSU_MFSPR 195
+#define POWER9_PME_PM_MRK_DPTEG_FROM_L3_1_ECO_SHR 196
+#define POWER9_PME_PM_VSU_DP_FSQRT_FDIV 197
+#define POWER9_PME_PM_IPTEG_FROM_L3_1_ECO_SHR 198
+#define POWER9_PME_PM_L3_P0_LCO_DATA 199
+#define POWER9_PME_PM_RUN_INST_CMPL 200
+#define POWER9_PME_PM_MRK_DATA_FROM_OFF_CHIP_CACHE 201
+#define POWER9_PME_PM_MRK_TEND_FAIL 202
+#define POWER9_PME_PM_MRK_VSU_FIN 203
+#define POWER9_PME_PM_DATA_FROM_L3_1_ECO_MOD 204
+#define POWER9_PME_PM_RUN_SPURR 205
+#define POWER9_PME_PM_ST_CAUSED_FAIL 206
+#define POWER9_PME_PM_SNOOP_TLBIE 207
+#define POWER9_PME_PM_PMC1_SAVED 208
+#define POWER9_PME_PM_DATA_FROM_L3MISS 209
+#define POWER9_PME_PM_DATA_FROM_ON_CHIP_CACHE 210
+#define POWER9_PME_PM_DTLB_MISS_16G 211
+#define POWER9_PME_PM_MRK_DPTEG_FROM_DMEM 212
+#define POWER9_PME_PM_ICT_NOSLOT_IC_L3MISS 213
+#define POWER9_PME_PM_FLUSH 214
+#define POWER9_PME_PM_LSU_FLUSH_OTHER 215
+#define POWER9_PME_PM_LS1_LAUNCH_HELD_PREF 216
+#define POWER9_PME_PM_L2_LD_HIT 217
+#define POWER9_PME_PM_LSU2_VECTOR_LD_FIN 218
+#define POWER9_PME_PM_LSU_FLUSH_EMSH 219
+#define POWER9_PME_PM_IC_PREF_REQ 220
+#define POWER9_PME_PM_DPTEG_FROM_L2_1_SHR 221
+#define POWER9_PME_PM_XLATE_RADIX_MODE 222
+#define POWER9_PME_PM_L3_LD_HIT 223
+#define POWER9_PME_PM_DARQ_7_9_ENTRIES 224
+#define POWER9_PME_PM_CMPLU_STALL_EXEC_UNIT 225
+#define POWER9_PME_PM_DISP_HELD 226
+#define POWER9_PME_PM_TM_FAIL_CONF_TM 227
+#define POWER9_PME_PM_LS0_DC_COLLISIONS 228
+#define POWER9_PME_PM_L2_LD 229
+#define POWER9_PME_PM_BTAC_GOOD_RESULT 230
+#define POWER9_PME_PM_TEND_PEND_CYC 231
+#define POWER9_PME_PM_MRK_DCACHE_RELOAD_INTV 232
+#define POWER9_PME_PM_DISP_HELD_HB_FULL 233
+#define POWER9_PME_PM_TM_TRESUME 234
+#define POWER9_PME_PM_MRK_LSU_FLUSH_SAO 235
+#define POWER9_PME_PM_LS0_TM_DISALLOW 236
+#define POWER9_PME_PM_DPTEG_FROM_OFF_CHIP_CACHE 237
+#define POWER9_PME_PM_RC0_BUSY 238
+#define POWER9_PME_PM_LSU1_TM_L1_HIT 239
+#define POWER9_PME_PM_TB_BIT_TRANS 240
+#define POWER9_PME_PM_DPTEG_FROM_L2_NO_CONFLICT 241
+#define POWER9_PME_PM_MRK_DPTEG_FROM_L3_1_MOD 242
+#define POWER9_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT 243
+#define POWER9_PME_PM_MRK_DATA_FROM_LL4_CYC 244
+#define POWER9_PME_PM_INST_FROM_OFF_CHIP_CACHE 245
+#define POWER9_PME_PM_L3_CO_L31 246
+#define POWER9_PME_PM_CMPLU_STALL_CRYPTO 247
+#define POWER9_PME_PM_RADIX_PWC_L1_PDE_FROM_L3 248
+#define POWER9_PME_PM_ICT_EMPTY_CYC 249
+#define POWER9_PME_PM_BR_UNCOND 250
+#define POWER9_PME_PM_DERAT_MISS_2M 251
+#define POWER9_PME_PM_PMC4_REWIND 252
+#define POWER9_PME_PM_L2_RCLD_DISP 253
+#define POWER9_PME_PM_CMPLU_STALL_DMISS_L2L3_CONFLICT 254
+#define POWER9_PME_PM_TAKEN_BR_MPRED_CMPL 255
+#define POWER9_PME_PM_THRD_PRIO_2_3_CYC 256
+#define POWER9_PME_PM_DATA_FROM_DL4 257
+#define POWER9_PME_PM_CMPLU_STALL_DPLONG 258
+#define POWER9_PME_PM_IC_DEMAND_L2_BHT_REDIRECT 259
+#define POWER9_PME_PM_MRK_FAB_RSP_BKILL 260
+#define POWER9_PME_PM_LSU_DERAT_MISS 261
+#define POWER9_PME_PM_IC_PREF_CANCEL_L2 262
+#define POWER9_PME_PM_MRK_NTC_CYC 263
+#define POWER9_PME_PM_STCX_FIN 264
+#define POWER9_PME_PM_MRK_DATA_FROM_L3_MEPF 265
+#define POWER9_PME_PM_DC_PREF_FUZZY_CONF 266
+#define POWER9_PME_PM_MULT_MRK 267
+#define POWER9_PME_PM_LSU_FLUSH_LARX_STCX 268
+#define POWER9_PME_PM_L3_P1_LCO_NO_DATA 269
+#define POWER9_PME_PM_TM_TABORT_TRECLAIM 270
+#define POWER9_PME_PM_MRK_DATA_FROM_L2_MEPF_CYC 271
+#define POWER9_PME_PM_BR_PRED_CCACHE 272
+#define POWER9_PME_PM_L3_P1_LCO_DATA 273
+#define POWER9_PME_PM_LINK_STACK_WRONG_ADD_PRED 274
+#define POWER9_PME_PM_MRK_DPTEG_FROM_L3 275
+#define POWER9_PME_PM_MRK_ST_CMPL_INT 276
+#define POWER9_PME_PM_FLUSH_HB_RESTORE_CYC 277
+#define POWER9_PME_PM_LS1_PTE_TABLEWALK_CYC 278
+#define POWER9_PME_PM_L3_CI_USAGE 279
+#define POWER9_PME_PM_MRK_DATA_FROM_L3MISS 280
+#define POWER9_PME_PM_DPTEG_FROM_DL4 281
+#define POWER9_PME_PM_MRK_STCX_FIN 282
+#define POWER9_PME_PM_MRK_LSU_FLUSH_UE 283
+#define POWER9_PME_PM_MRK_DATA_FROM_MEMORY 284
+#define POWER9_PME_PM_GRP_PUMP_MPRED_RTY 285
+#define POWER9_PME_PM_DPTEG_FROM_L3_1_ECO_SHR 286
+#define POWER9_PME_PM_FLUSH_DISP_TLBIE 287
+#define POWER9_PME_PM_DPTEG_FROM_L3MISS 288
+#define POWER9_PME_PM_L3_GRP_GUESS_CORRECT 289
+#define POWER9_PME_PM_IC_INVALIDATE 290
+#define POWER9_PME_PM_DERAT_MISS_16G 291
+#define POWER9_PME_PM_SYS_PUMP_MPRED_RTY 292
+#define POWER9_PME_PM_LMQ_MERGE 293
+#define POWER9_PME_PM_IPTEG_FROM_LMEM 294
+#define POWER9_PME_PM_L3_LAT_CI_HIT 295
+#define POWER9_PME_PM_LSU1_VECTOR_ST_FIN 296
+#define POWER9_PME_PM_IC_DEMAND_L2_BR_REDIRECT 297
+#define POWER9_PME_PM_INST_FROM_LMEM 298
+#define POWER9_PME_PM_MRK_DATA_FROM_RL4 299
+#define POWER9_PME_PM_MRK_DTLB_MISS_4K 300
+#define POWER9_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT 301
+#define POWER9_PME_PM_CMPLU_STALL_NTC_FLUSH 302
+#define POWER9_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC 303
+#define POWER9_PME_PM_DARQ_0_3_ENTRIES 304
+#define POWER9_PME_PM_DATA_FROM_L3MISS_MOD 305
+#define POWER9_PME_PM_MRK_DATA_FROM_L2_1_SHR_CYC 306
+#define POWER9_PME_PM_TAGE_OVERRIDE_WRONG 307
+#define POWER9_PME_PM_L2_LD_MISS 308
+#define POWER9_PME_PM_EAT_FULL_CYC 309
+#define POWER9_PME_PM_CMPLU_STALL_SPEC_FINISH 310
+#define POWER9_PME_PM_MRK_LSU_FLUSH_LARX_STCX 311
+#define POWER9_PME_PM_THRESH_EXC_128 312
+#define POWER9_PME_PM_LMQ_EMPTY_CYC 313
+#define POWER9_PME_PM_RADIX_PWC_L2_PDE_FROM_L3 314
+#define POWER9_PME_PM_MRK_IC_MISS 315
+#define POWER9_PME_PM_L3_P1_GRP_PUMP 316
+#define POWER9_PME_PM_CMPLU_STALL_TEND 317
+#define POWER9_PME_PM_PUMP_MPRED 318
+#define POWER9_PME_PM_INST_GRP_PUMP_MPRED 319
+#define POWER9_PME_PM_L1_PREF 320
+#define POWER9_PME_PM_MRK_DATA_FROM_LMEM_CYC 321
+#define POWER9_PME_PM_LSU_FLUSH_ATOMIC 322
+#define POWER9_PME_PM_L2_DISP_ALL_L2MISS 323
+#define POWER9_PME_PM_DATA_FROM_MEMORY 324
+#define POWER9_PME_PM_IPTEG_FROM_L3_1_ECO_MOD 325
+#define POWER9_PME_PM_ISIDE_DISP_FAIL_ADDR 326
+#define POWER9_PME_PM_CMPLU_STALL_HWSYNC 327
+#define POWER9_PME_PM_DATA_FROM_L3 328
+#define POWER9_PME_PM_PMC2_OVERFLOW 329
+#define POWER9_PME_PM_LSU0_SRQ_S0_VALID_CYC 330
+#define POWER9_PME_PM_DPTEG_FROM_LMEM 331
+#define POWER9_PME_PM_IPTEG_FROM_ON_CHIP_CACHE 332
+#define POWER9_PME_PM_LSU1_SET_MPRED 333
+#define POWER9_PME_PM_DATA_FROM_L3_1_ECO_SHR 334
+#define POWER9_PME_PM_INST_FROM_MEMORY 335
+#define POWER9_PME_PM_L3_P1_LCO_RTY 336
+#define POWER9_PME_PM_DATA_FROM_L2_1_SHR 337
+#define POWER9_PME_PM_FLUSH_LSU 338
+#define POWER9_PME_PM_CMPLU_STALL_FXLONG 339
+#define POWER9_PME_PM_CMPLU_STALL_DMISS_LMEM 340
+#define POWER9_PME_PM_SNP_TM_HIT_M 341
+#define POWER9_PME_PM_INST_GRP_PUMP_MPRED_RTY 342
+#define POWER9_PME_PM_L2_INST_MISS 343
+#define POWER9_PME_PM_CMPLU_STALL_ERAT_MISS 344
+#define POWER9_PME_PM_MRK_L2_RC_DONE 345
+#define POWER9_PME_PM_INST_FROM_L3_1_SHR 346
+#define POWER9_PME_PM_RADIX_PWC_L4_PDE_FROM_L2 347
+#define POWER9_PME_PM_MRK_DATA_FROM_L3_1_MOD 348
+#define POWER9_PME_PM_CO0_BUSY 349
+#define POWER9_PME_PM_CMPLU_STALL_STORE_DATA 350
+#define POWER9_PME_PM_INST_FROM_RMEM 351
+#define POWER9_PME_PM_SYNC_MRK_BR_LINK 352
+#define POWER9_PME_PM_L3_LD_PREF 353
+#define POWER9_PME_PM_DISP_CLB_HELD_TLBIE 354
+#define POWER9_PME_PM_DPTEG_FROM_ON_CHIP_CACHE 355
+#define POWER9_PME_PM_MRK_DATA_FROM_L3_MEPF_CYC 356
+#define POWER9_PME_PM_LS0_UNALIGNED_LD 357
+#define POWER9_PME_PM_MRK_DATA_FROM_DMEM_CYC 358
+#define POWER9_PME_PM_SN_HIT 359
+#define POWER9_PME_PM_L3_LOC_GUESS_CORRECT 360
+#define POWER9_PME_PM_MRK_INST_FROM_L3MISS 361
+#define POWER9_PME_PM_DECODE_FUSION_EXT_ADD 362
+#define POWER9_PME_PM_INST_FROM_DL4 363
+#define POWER9_PME_PM_DC_PREF_XCONS_ALLOC 364
+#define POWER9_PME_PM_MRK_DPTEG_FROM_MEMORY 365
+#define POWER9_PME_PM_IC_PREF_CANCEL_PAGE 366
+#define POWER9_PME_PM_RADIX_PWC_L3_PTE_FROM_L3 367
+#define POWER9_PME_PM_L3_GRP_GUESS_WRONG_LOW 368
+#define POWER9_PME_PM_TM_FAIL_SELF 369
+#define POWER9_PME_PM_L3_P1_SYS_PUMP 370
+#define POWER9_PME_PM_CMPLU_STALL_RFID 371
+#define POWER9_PME_PM_BR_2PATH 372
+#define POWER9_PME_PM_RADIX_PWC_L4_PTE_FROM_L3MISS 373
+#define POWER9_PME_PM_DPTEG_FROM_L2MISS 374
+#define POWER9_PME_PM_TM_TX_PASS_RUN_INST 375
+#define POWER9_PME_PM_L1_ICACHE_RELOADED_PREF 376
+#define POWER9_PME_PM_THRESH_EXC_4096 377
+#define POWER9_PME_PM_IERAT_RELOAD_64K 378
+#define POWER9_PME_PM_LSU0_TM_L1_MISS 379
+#define POWER9_PME_PM_MEM_LOC_THRESH_LSU_MED 380
+#define POWER9_PME_PM_PMC3_REWIND 381
+#define POWER9_PME_PM_ST_FWD 382
+#define POWER9_PME_PM_TM_FAIL_TX_CONFLICT 383
+#define POWER9_PME_PM_SYNC_MRK_L2MISS 384
+#define POWER9_PME_PM_ISU0_ISS_HOLD_ALL 385
+#define POWER9_PME_PM_MRK_FAB_RSP_DCLAIM_CYC 386
+#define POWER9_PME_PM_DATA_FROM_L2 387
+#define POWER9_PME_PM_MRK_DATA_FROM_RL2L3_MOD 388
+#define POWER9_PME_PM_ISQ_0_8_ENTRIES 389
+#define POWER9_PME_PM_L3_CO_MEPF 390
+#define POWER9_PME_PM_LINK_STACK_INVALID_PTR 391
+#define POWER9_PME_PM_IPTEG_FROM_L2_1_MOD 392
+#define POWER9_PME_PM_TM_ST_CAUSED_FAIL 393
+#define POWER9_PME_PM_LD_REF_L1 394
+#define POWER9_PME_PM_TM_FAIL_NON_TX_CONFLICT 395
+#define POWER9_PME_PM_GRP_PUMP_CPRED 396
+#define POWER9_PME_PM_INST_FROM_L3_NO_CONFLICT 397
+#define POWER9_PME_PM_DC_PREF_STRIDED_CONF 398
+#define POWER9_PME_PM_THRD_PRIO_6_7_CYC 399
+#define POWER9_PME_PM_RADIX_PWC_L4_PDE_FROM_L3 400
+#define POWER9_PME_PM_L3_PF_OFF_CHIP_MEM 401
+#define POWER9_PME_PM_L3_CO_MEM 402
+#define POWER9_PME_PM_DECODE_HOLD_ICT_FULL 403
+#define POWER9_PME_PM_CMPLU_STALL_DFLONG 404
+#define POWER9_PME_PM_LD_MISS_L1 405
+#define POWER9_PME_PM_DATA_FROM_RL2L3_MOD 406
+#define POWER9_PME_PM_L3_WI0_BUSY 407
+#define POWER9_PME_PM_LSU_SRQ_FULL_CYC 408
+#define POWER9_PME_PM_TABLEWALK_CYC 409
+#define POWER9_PME_PM_MRK_DATA_FROM_MEMORY_CYC 410
+#define POWER9_PME_PM_IPTEG_FROM_OFF_CHIP_CACHE 411
+#define POWER9_PME_PM_RADIX_PWC_L1_PDE_FROM_L3MISS 412
+#define POWER9_PME_PM_CMPLU_STALL_SYS_CALL 413
+#define POWER9_PME_PM_LSU_FLUSH_RELAUNCH_MISS 414
+#define POWER9_PME_PM_DPTEG_FROM_L3_1_ECO_MOD 415
+#define POWER9_PME_PM_PMC5_OVERFLOW 416
+#define POWER9_PME_PM_LS1_UNALIGNED_ST 417
+#define POWER9_PME_PM_ICT_NOSLOT_DISP_HELD_SYNC 418
+#define POWER9_PME_PM_CMPLU_STALL_THRD 419
+#define POWER9_PME_PM_PMC3_SAVED 420
+#define POWER9_PME_PM_MRK_DERAT_MISS 421
+#define POWER9_PME_PM_RADIX_PWC_L3_HIT 422
+#define POWER9_PME_PM_RADIX_PWC_L2_PTE_FROM_L3MISS 423
+#define POWER9_PME_PM_RUN_CYC_SMT4_MODE 424
+#define POWER9_PME_PM_DATA_FROM_RMEM 425
+#define POWER9_PME_PM_BR_MPRED_LSTACK 426
+#define POWER9_PME_PM_PROBE_NOP_DISP 427
+#define POWER9_PME_PM_DPTEG_FROM_L3_MEPF 428
+#define POWER9_PME_PM_INST_FROM_L3MISS_MOD 429
+#define POWER9_PME_PM_DUMMY1_REMOVE_ME 430
+#define POWER9_PME_PM_MRK_DATA_FROM_DL4 431
+#define POWER9_PME_PM_MRK_DATA_FROM_RL2L3_MOD_CYC 432
+#define POWER9_PME_PM_IPTEG_FROM_L3_1_SHR 433
+#define POWER9_PME_PM_MRK_DATA_FROM_L3_1_ECO_SHR 434
+#define POWER9_PME_PM_DTLB_MISS_2M 435
+#define POWER9_PME_PM_TM_RST_SC 436
+#define POWER9_PME_PM_LSU_NCST 437
+#define POWER9_PME_PM_DATA_SYS_PUMP_MPRED_RTY 438
+#define POWER9_PME_PM_THRESH_ACC 439
+#define POWER9_PME_PM_ISU3_ISS_HOLD_ALL 440
+#define POWER9_PME_PM_LSU0_L1_CAM_CANCEL 441
+#define POWER9_PME_PM_MRK_FAB_RSP_BKILL_CYC 442
+#define POWER9_PME_PM_MRK_DPTEG_FROM_L3_MEPF 443
+#define POWER9_PME_PM_DARQ_STORE_REJECT 444
+#define POWER9_PME_PM_DPTEG_FROM_L3_NO_CONFLICT 445
+#define POWER9_PME_PM_TM_TX_PASS_RUN_CYC 446
+#define POWER9_PME_PM_DTLB_MISS_4K 447
+#define POWER9_PME_PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC 448
+#define POWER9_PME_PM_LS0_PTE_TABLEWALK_CYC 449
+#define POWER9_PME_PM_PMC4_SAVED 450
+#define POWER9_PME_PM_SNP_TM_HIT_T 451
+#define POWER9_PME_PM_MRK_BR_2PATH 452
+#define POWER9_PME_PM_LSU_FLUSH_CI 453
+#define POWER9_PME_PM_FLUSH_MPRED 454
+#define POWER9_PME_PM_CMPLU_STALL_ST_FWD 455
+#define POWER9_PME_PM_DTLB_MISS 456
+#define POWER9_PME_PM_MRK_L2_TM_REQ_ABORT 457
+#define POWER9_PME_PM_TM_NESTED_TEND 458
+#define POWER9_PME_PM_CMPLU_STALL_PM 459
+#define POWER9_PME_PM_CMPLU_STALL_ISYNC 460
+#define POWER9_PME_PM_MRK_DTLB_MISS_1G 461
+#define POWER9_PME_PM_L3_SYS_GUESS_CORRECT 462
+#define POWER9_PME_PM_L2_CASTOUT_SHR 463
+#define POWER9_PME_PM_CMPLU_STALL_DMISS_L2L3 464
+#define POWER9_PME_PM_LS2_UNALIGNED_ST 465
+#define POWER9_PME_PM_MRK_DPTEG_FROM_L2MISS 466
+#define POWER9_PME_PM_THRESH_EXC_32 467
+#define POWER9_PME_PM_TM_TSUSPEND 468
+#define POWER9_PME_PM_DATA_FROM_DL2L3_SHR 469
+#define POWER9_PME_PM_MRK_DATA_FROM_L3_DISP_CONFLICT 470
+#define POWER9_PME_PM_MRK_DATA_FROM_L3_1_ECO_SHR_CYC 471
+#define POWER9_PME_PM_THRESH_EXC_1024 472
+#define POWER9_PME_PM_ST_FIN 473
+#define POWER9_PME_PM_TM_LD_CAUSED_FAIL 474
+#define POWER9_PME_PM_SRQ_SYNC_CYC 475
+#define POWER9_PME_PM_IFETCH_THROTTLE 476
+#define POWER9_PME_PM_L3_SW_PREF 477
+#define POWER9_PME_PM_LSU0_LDMX_FIN 478
+#define POWER9_PME_PM_L2_LOC_GUESS_WRONG 479
+#define POWER9_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC 480
+#define POWER9_PME_PM_MRK_DPTEG_FROM_ON_CHIP_CACHE 481
+#define POWER9_PME_PM_L3_P1_CO_RTY 482
+#define POWER9_PME_PM_MRK_STCX_FAIL 483
+#define POWER9_PME_PM_LARX_FIN 484
+#define POWER9_PME_PM_RADIX_PWC_L2_PTE_FROM_L3 485
+#define POWER9_PME_PM_LSU3_L1_CAM_CANCEL 486
+#define POWER9_PME_PM_IC_PREF_CANCEL_HIT 487
+#define POWER9_PME_PM_CMPLU_STALL_EIEIO 488
+#define POWER9_PME_PM_CMPLU_STALL_VDP 489
+#define POWER9_PME_PM_DERAT_MISS_1G 490
+#define POWER9_PME_PM_DATA_PUMP_CPRED 491
+#define POWER9_PME_PM_DPTEG_FROM_L2_MEPF 492
+#define POWER9_PME_PM_BR_MPRED_TAKEN_CR 493
+#define POWER9_PME_PM_MRK_BRU_FIN 494
+#define POWER9_PME_PM_MRK_DPTEG_FROM_DL4 495
+#define POWER9_PME_PM_SHL_ST_DEP_CREATED 496
+#define POWER9_PME_PM_DPTEG_FROM_L3_1_SHR 497
+#define POWER9_PME_PM_DATA_FROM_RL4 498
+#define POWER9_PME_PM_XLATE_MISS 499
+#define POWER9_PME_PM_CMPLU_STALL_SRQ_FULL 500
+#define POWER9_PME_PM_SN0_BUSY 501
+#define POWER9_PME_PM_CMPLU_STALL_NESTED_TBEGIN 502
+#define POWER9_PME_PM_ST_CMPL 503
+#define POWER9_PME_PM_DPTEG_FROM_DL2L3_SHR 504
+#define POWER9_PME_PM_DECODE_FUSION_CONST_GEN 505
+#define POWER9_PME_PM_L2_LOC_GUESS_CORRECT 506
+#define POWER9_PME_PM_INST_FROM_L3_1_ECO_SHR 507
+#define POWER9_PME_PM_XLATE_HPT_MODE 508
+#define POWER9_PME_PM_CMPLU_STALL_LSU_FIN 509
+#define POWER9_PME_PM_THRESH_EXC_64 510
+#define POWER9_PME_PM_MRK_DATA_FROM_DL4_CYC 511
+#define POWER9_PME_PM_DARQ_STORE_XMIT 512
+#define POWER9_PME_PM_DATA_TABLEWALK_CYC 513
+#define POWER9_PME_PM_L2_RC_ST_DONE 514
+#define POWER9_PME_PM_TMA_REQ_L2 515
+#define POWER9_PME_PM_INST_FROM_ON_CHIP_CACHE 516
+#define POWER9_PME_PM_SLB_TABLEWALK_CYC 517
+#define POWER9_PME_PM_MRK_DATA_FROM_RMEM 518
+#define POWER9_PME_PM_L3_PF_MISS_L3 519
+#define POWER9_PME_PM_L3_CI_MISS 520
+#define POWER9_PME_PM_L2_RCLD_DISP_FAIL_ADDR 521
+#define POWER9_PME_PM_DERAT_MISS_4K 522
+#define POWER9_PME_PM_ISIDE_MRU_TOUCH 523
+#define POWER9_PME_PM_MRK_RUN_CYC 524
+#define POWER9_PME_PM_L3_P0_CO_RTY 525
+#define POWER9_PME_PM_BR_MPRED_CMPL 526
+#define POWER9_PME_PM_BR_MPRED_TAKEN_TA 527
+#define POWER9_PME_PM_DISP_HELD_TBEGIN 528
+#define POWER9_PME_PM_DPTEG_FROM_RL2L3_MOD 529
+#define POWER9_PME_PM_FLUSH_DISP_SB 530
+#define POWER9_PME_PM_L2_CHIP_PUMP 531
+#define POWER9_PME_PM_L2_DC_INV 532
+#define POWER9_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC 533
+#define POWER9_PME_PM_MRK_DPTEG_FROM_L3_1_SHR 534
+#define POWER9_PME_PM_MRK_DERAT_MISS_2M 535
+#define POWER9_PME_PM_MRK_ST_DONE_L2 536
+#define POWER9_PME_PM_MRK_DATA_FROM_L3_1_ECO_MOD 537
+#define POWER9_PME_PM_IPTEG_FROM_RMEM 538
+#define POWER9_PME_PM_MRK_LSU_FLUSH_EMSH 539
+#define POWER9_PME_PM_BR_PRED_LSTACK 540
+#define POWER9_PME_PM_L3_P0_CO_MEM 541
+#define POWER9_PME_PM_IPTEG_FROM_L2_MEPF 542
+#define POWER9_PME_PM_LS0_ERAT_MISS_PREF 543
+#define POWER9_PME_PM_RD_HIT_PF 544
+#define POWER9_PME_PM_DECODE_FUSION_LD_ST_DISP 545
+#define POWER9_PME_PM_CMPLU_STALL_NTC_DISP_FIN 546
+#define POWER9_PME_PM_ICT_NOSLOT_CYC 547
+#define POWER9_PME_PM_DERAT_MISS_16M 548
+#define POWER9_PME_PM_IC_MISS_ICBI 549
+#define POWER9_PME_PM_TAGE_OVERRIDE_WRONG_SPEC 550
+#define POWER9_PME_PM_ICT_NOSLOT_DISP_HELD_TBEGIN 551
+#define POWER9_PME_PM_MRK_BR_TAKEN_CMPL 552
+#define POWER9_PME_PM_CMPLU_STALL_VFXU 553
+#define POWER9_PME_PM_DATA_GRP_PUMP_MPRED_RTY 554
+#define POWER9_PME_PM_INST_FROM_L3 555
+#define POWER9_PME_PM_ITLB_MISS 556
+#define POWER9_PME_PM_MRK_DPTEG_FROM_RL2L3_MOD 557
+#define POWER9_PME_PM_LSU2_TM_L1_MISS 558
+#define POWER9_PME_PM_L3_WI_USAGE 559
+#define POWER9_PME_PM_L2_SN_M_WR_DONE 560
+#define POWER9_PME_PM_DISP_HELD_SYNC_HOLD 561
+#define POWER9_PME_PM_MRK_DPTEG_FROM_L2_1_SHR 562
+#define POWER9_PME_PM_MEM_PREF 563
+#define POWER9_PME_PM_L2_SN_M_RD_DONE 564
+#define POWER9_PME_PM_LS0_UNALIGNED_ST 565
+#define POWER9_PME_PM_DC_PREF_CONS_ALLOC 566
+#define POWER9_PME_PM_MRK_DERAT_MISS_16G 567
+#define POWER9_PME_PM_IPTEG_FROM_L2 568
+#define POWER9_PME_PM_ANY_THRD_RUN_CYC 569
+#define POWER9_PME_PM_MRK_PROBE_NOP_CMPL 570
+#define POWER9_PME_PM_BANK_CONFLICT 571
+#define POWER9_PME_PM_INST_SYS_PUMP_MPRED 572
+#define POWER9_PME_PM_NON_DATA_STORE 573
+#define POWER9_PME_PM_DC_PREF_CONF 574
+#define POWER9_PME_PM_BTAC_BAD_RESULT 575
+#define POWER9_PME_PM_LSU_LMQ_FULL_CYC 576
+#define POWER9_PME_PM_NON_MATH_FLOP_CMPL 577
+#define POWER9_PME_PM_MRK_LD_MISS_L1_CYC 578
+#define POWER9_PME_PM_MRK_DATA_FROM_L2_CYC 579
+#define POWER9_PME_PM_FXU_1PLUS_BUSY 580
+#define POWER9_PME_PM_CMPLU_STALL_DP 581
+#define POWER9_PME_PM_MRK_DATA_FROM_L3_1_MOD_CYC 582
+#define POWER9_PME_PM_SYNC_MRK_L2HIT 583
+#define POWER9_PME_PM_MRK_DATA_FROM_RMEM_CYC 584
+#define POWER9_PME_PM_ISU1_ISS_HOLD_ALL 585
+#define POWER9_PME_PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT 586
+#define POWER9_PME_PM_MRK_FAB_RSP_RWITM_RTY 587
+#define POWER9_PME_PM_L3_P3_LCO_RTY 588
+#define POWER9_PME_PM_PUMP_CPRED 589
+#define POWER9_PME_PM_LS3_TM_DISALLOW 590
+#define POWER9_PME_PM_SN_INVL 591
+#define POWER9_PME_PM_TM_LD_CONF 592
+#define POWER9_PME_PM_LD_MISS_L1_FIN 593
+#define POWER9_PME_PM_SYNC_MRK_PROBE_NOP 594
+#define POWER9_PME_PM_RUN_CYC 595
+#define POWER9_PME_PM_SYS_PUMP_MPRED 596
+#define POWER9_PME_PM_DATA_FROM_OFF_CHIP_CACHE 597
+#define POWER9_PME_PM_TM_NESTED_TBEGIN 598
+#define POWER9_PME_PM_FLUSH_COMPLETION 599
+#define POWER9_PME_PM_ST_MISS_L1 600
+#define POWER9_PME_PM_IPTEG_FROM_L2MISS 601
+#define POWER9_PME_PM_LSU3_TM_L1_MISS 602
+#define POWER9_PME_PM_L3_CO 603
+#define POWER9_PME_PM_MRK_STALL_CMPLU_CYC 604
+#define POWER9_PME_PM_INST_FROM_DL2L3_SHR 605
+#define POWER9_PME_PM_SCALAR_FLOP_CMPL 606
+#define POWER9_PME_PM_LRQ_REJECT 607
+#define POWER9_PME_PM_4FLOP_CMPL 608
+#define POWER9_PME_PM_MRK_DPTEG_FROM_RMEM 609
+#define POWER9_PME_PM_LD_CMPL 610
+#define POWER9_PME_PM_DATA_FROM_L3_MEPF 611
+#define POWER9_PME_PM_L1PF_L2MEMACC 612
+#define POWER9_PME_PM_INST_FROM_L3MISS 613
+#define POWER9_PME_PM_MRK_LSU_FLUSH_LHS 614
+#define POWER9_PME_PM_EE_OFF_EXT_INT 615
+#define POWER9_PME_PM_TM_ST_CONF 616
+#define POWER9_PME_PM_PMC6_OVERFLOW 617
+#define POWER9_PME_PM_INST_FROM_DL2L3_MOD 618
+#define POWER9_PME_PM_MRK_INST_CMPL 619
+#define POWER9_PME_PM_TAGE_CORRECT_TAKEN_CMPL 620
+#define POWER9_PME_PM_MRK_L1_ICACHE_MISS 621
+#define POWER9_PME_PM_TLB_MISS 622
+#define POWER9_PME_PM_L2_RCLD_DISP_FAIL_OTHER 623
+#define POWER9_PME_PM_FXU_BUSY 624
+#define POWER9_PME_PM_DATA_FROM_L3_DISP_CONFLICT 625
+#define POWER9_PME_PM_INST_FROM_L3_1_MOD 626
+#define POWER9_PME_PM_LSU_REJECT_LMQ_FULL 627
+#define POWER9_PME_PM_CO_DISP_FAIL 628
+#define POWER9_PME_PM_L3_TRANS_PF 629
+#define POWER9_PME_PM_MRK_ST_NEST 630
+#define POWER9_PME_PM_LSU1_L1_CAM_CANCEL 631
+#define POWER9_PME_PM_INST_CHIP_PUMP_CPRED 632
+#define POWER9_PME_PM_LSU3_VECTOR_ST_FIN 633
+#define POWER9_PME_PM_MRK_DPTEG_FROM_L2_1_MOD 634
+#define POWER9_PME_PM_IBUF_FULL_CYC 635
+#define POWER9_PME_PM_8FLOP_CMPL 636
+#define POWER9_PME_PM_MRK_DATA_FROM_DL2L3_SHR_CYC 637
+#define POWER9_PME_PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE 638
+#define POWER9_PME_PM_ICT_NOSLOT_IC_L3 639
+#define POWER9_PME_PM_CMPLU_STALL_LWSYNC 640
+#define POWER9_PME_PM_RADIX_PWC_L2_PDE_FROM_L2 641
+#define POWER9_PME_PM_MRK_DATA_FROM_RL2L3_SHR_CYC 642
+#define POWER9_PME_PM_L3_SN0_BUSY 643
+#define POWER9_PME_PM_TM_OUTER_TBEGIN_DISP 644
+#define POWER9_PME_PM_GRP_PUMP_MPRED 645
+#define POWER9_PME_PM_SRQ_EMPTY_CYC 646
+#define POWER9_PME_PM_LSU_REJECT_LHS 647
+#define POWER9_PME_PM_IPTEG_FROM_L3_MEPF 648
+#define POWER9_PME_PM_MRK_DATA_FROM_LMEM 649
+#define POWER9_PME_PM_L3_P1_CO_MEM 650
+#define POWER9_PME_PM_FREQ_DOWN 651
+#define POWER9_PME_PM_L3_CINJ 652
+#define POWER9_PME_PM_L3_P0_PF_RTY 653
+#define POWER9_PME_PM_IPTEG_FROM_DL2L3_MOD 654
+#define POWER9_PME_PM_MRK_INST_ISSUED 655
+#define POWER9_PME_PM_INST_FROM_RL2L3_SHR 656
+#define POWER9_PME_PM_LSU_STCX_FAIL 657
+#define POWER9_PME_PM_L3_P1_NODE_PUMP 658
+#define POWER9_PME_PM_MEM_RWITM 659
+#define POWER9_PME_PM_DP_QP_FLOP_CMPL 660
+#define POWER9_PME_PM_RUN_PURR 661
+#define POWER9_PME_PM_CMPLU_STALL_LMQ_FULL 662
+#define POWER9_PME_PM_CMPLU_STALL_VDPLONG 663
+#define POWER9_PME_PM_LSU2_TM_L1_HIT 664
+#define POWER9_PME_PM_MRK_DATA_FROM_L3 665
+#define POWER9_PME_PM_CMPLU_STALL_MTFPSCR 666
+#define POWER9_PME_PM_STALL_END_ICT_EMPTY 667
+#define POWER9_PME_PM_L3_P1_CO_L31 668
+#define POWER9_PME_PM_CMPLU_STALL_DCACHE_MISS 669
+#define POWER9_PME_PM_DPTEG_FROM_DL2L3_MOD 670
+#define POWER9_PME_PM_INST_FROM_L3_MEPF 671
+#define POWER9_PME_PM_L1_DCACHE_RELOADED_ALL 672
+#define POWER9_PME_PM_DATA_GRP_PUMP_CPRED 673
+#define POWER9_PME_PM_MRK_DERAT_MISS_64K 674
+#define POWER9_PME_PM_L2_ST_MISS 675
+#define POWER9_PME_PM_L3_PF_OFF_CHIP_CACHE 676
+#define POWER9_PME_PM_RADIX_PWC_L3_PTE_FROM_L3MISS 677
+#define POWER9_PME_PM_LWSYNC 678
+#define POWER9_PME_PM_LS3_UNALIGNED_LD 679
+#define POWER9_PME_PM_L3_RD0_BUSY 680
+#define POWER9_PME_PM_LINK_STACK_CORRECT 681
+#define POWER9_PME_PM_MRK_DTLB_MISS 682
+#define POWER9_PME_PM_INST_IMC_MATCH_CMPL 683
+#define POWER9_PME_PM_LS1_ERAT_MISS_PREF 684
+#define POWER9_PME_PM_L3_CO0_BUSY 685
+#define POWER9_PME_PM_BFU_BUSY 686
+#define POWER9_PME_PM_L2_SYS_GUESS_CORRECT 687
+#define POWER9_PME_PM_L1_SW_PREF 688
+#define POWER9_PME_PM_MRK_DATA_FROM_LL4 689
+#define POWER9_PME_PM_MRK_INST_FIN 690
+#define POWER9_PME_PM_SYNC_MRK_L3MISS 691
+#define POWER9_PME_PM_LSU1_STORE_REJECT 692
+#define POWER9_PME_PM_CHIP_PUMP_CPRED 693
+#define POWER9_PME_PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC 694
+#define POWER9_PME_PM_DATA_STORE 695
+#define POWER9_PME_PM_LS1_UNALIGNED_LD 696
+#define POWER9_PME_PM_TM_TRANS_RUN_INST 697
+#define POWER9_PME_PM_IC_MISS_CMPL 698
+#define POWER9_PME_PM_THRESH_NOT_MET 699
+#define POWER9_PME_PM_DPTEG_FROM_L2 700
+#define POWER9_PME_PM_IPTEG_FROM_RL2L3_SHR 701
+#define POWER9_PME_PM_DPTEG_FROM_RMEM 702
+#define POWER9_PME_PM_L3_L2_CO_MISS 703
+#define POWER9_PME_PM_IPTEG_FROM_DMEM 704
+#define POWER9_PME_PM_MRK_DTLB_MISS_64K 705
+#define POWER9_PME_PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC 706
+#define POWER9_PME_PM_LSU_FIN 707
+#define POWER9_PME_PM_DATA_FROM_L2_DISP_CONFLICT_OTHER 708
+#define POWER9_PME_PM_MRK_DATA_FROM_ON_CHIP_CACHE 709
+#define POWER9_PME_PM_LSU_STCX 710
+#define POWER9_PME_PM_MRK_DATA_FROM_L2_1_MOD 711
+#define POWER9_PME_PM_VSU_NON_FLOP_CMPL 712
+#define POWER9_PME_PM_INST_FROM_L3_DISP_CONFLICT 713
+#define POWER9_PME_PM_MRK_DATA_FROM_L2_1_SHR 714
+#define POWER9_PME_PM_RADIX_PWC_L4_PTE_FROM_L3 715
+#define POWER9_PME_PM_TAGE_CORRECT 716
+#define POWER9_PME_PM_TM_FAV_CAUSED_FAIL 717
+#define POWER9_PME_PM_RADIX_PWC_L1_HIT 718
+#define POWER9_PME_PM_LSU0_LMQ_S0_VALID 719
+#define POWER9_PME_PM_BR_MPRED_CCACHE 720
+#define POWER9_PME_PM_L1_DEMAND_WRITE 721
+#define POWER9_PME_PM_CMPLU_STALL_FLUSH_ANY_THREAD 722
+#define POWER9_PME_PM_IPTEG_FROM_L3MISS 723
+#define POWER9_PME_PM_MRK_DTLB_MISS_16G 724
+#define POWER9_PME_PM_IPTEG_FROM_RL4 725
+#define POWER9_PME_PM_L2_RCST_DISP 726
+#define POWER9_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC 727
+#define POWER9_PME_PM_CMPLU_STALL 728
+#define POWER9_PME_PM_DISP_CLB_HELD_SB 729
+#define POWER9_PME_PM_L3_SN_USAGE 730
+#define POWER9_PME_PM_FLOP_CMPL 731
+#define POWER9_PME_PM_MRK_L2_RC_DISP 732
+#define POWER9_PME_PM_L3_PF_ON_CHIP_CACHE 733
+#define POWER9_PME_PM_IC_DEMAND_CYC 734
+#define POWER9_PME_PM_CO_USAGE 735
+#define POWER9_PME_PM_ISYNC 736
+#define POWER9_PME_PM_MEM_CO 737
+#define POWER9_PME_PM_NTC_ALL_FIN 738
+#define POWER9_PME_PM_CMPLU_STALL_EXCEPTION 739
+#define POWER9_PME_PM_LS0_LAUNCH_HELD_PREF 740
+#define POWER9_PME_PM_ICT_NOSLOT_BR_MPRED 741
+#define POWER9_PME_PM_MRK_BR_CMPL 742
+#define POWER9_PME_PM_ICT_NOSLOT_DISP_HELD 743
+#define POWER9_PME_PM_IC_PREF_WRITE 744
+#define POWER9_PME_PM_MRK_LSU_FLUSH_LHL_SHL 745
+#define POWER9_PME_PM_DTLB_MISS_1G 746
+#define POWER9_PME_PM_DATA_FROM_L2_NO_CONFLICT 747
+#define POWER9_PME_PM_MRK_DPTEG_FROM_L3MISS 748
+#define POWER9_PME_PM_BR_PRED 749
+#define POWER9_PME_PM_CMPLU_STALL_OTHER_CMPL 750
+#define POWER9_PME_PM_INST_FROM_DMEM 751
+#define POWER9_PME_PM_MRK_DPTEG_FROM_L2_NO_CONFLICT 752
+#define POWER9_PME_PM_DC_PREF_SW_ALLOC 753
+#define POWER9_PME_PM_L2_RCST_DISP_FAIL_OTHER 754
+#define POWER9_PME_PM_CMPLU_STALL_EMQ_FULL 755
+#define POWER9_PME_PM_MRK_INST_DECODED 756
+#define POWER9_PME_PM_IERAT_RELOAD_4K 757
+#define POWER9_PME_PM_CMPLU_STALL_LRQ_OTHER 758
+#define POWER9_PME_PM_INST_FROM_L3_1_ECO_MOD 759
+#define POWER9_PME_PM_L3_P0_CO_L31 760
+#define POWER9_PME_PM_NON_TM_RST_SC 761
+#define POWER9_PME_PM_RADIX_PWC_L4_PTE_FROM_L2 762
+#define POWER9_PME_PM_INST_SYS_PUMP_CPRED 763
+#define POWER9_PME_PM_DPTEG_FROM_DMEM 764
+#define POWER9_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 765
+#define POWER9_PME_PM_SYS_PUMP_CPRED 766
+#define POWER9_PME_PM_DTLB_MISS_64K 767
+#define POWER9_PME_PM_CMPLU_STALL_STCX 768
+#define POWER9_PME_PM_MRK_FAB_RSP_CLAIM_RTY 769
+#define POWER9_PME_PM_PARTIAL_ST_FIN 770
+#define POWER9_PME_PM_THRD_CONC_RUN_INST 771
+#define POWER9_PME_PM_CO_TM_SC_FOOTPRINT 772
+#define POWER9_PME_PM_MRK_LARX_FIN 773
+#define POWER9_PME_PM_L3_LOC_GUESS_WRONG 774
+#define POWER9_PME_PM_CMPLU_STALL_DMISS_L21_L31 775
+#define POWER9_PME_PM_SHL_ST_DISABLE 776
+#define POWER9_PME_PM_VSU_FIN 777
+#define POWER9_PME_PM_MRK_LSU_FLUSH_ATOMIC 778
+#define POWER9_PME_PM_L3_CI_HIT 779
+#define POWER9_PME_PM_CMPLU_STALL_DARQ 780
+#define POWER9_PME_PM_L3_PF_ON_CHIP_MEM 781
+#define POWER9_PME_PM_THRD_PRIO_0_1_CYC 782
+#define POWER9_PME_PM_DERAT_MISS_64K 783
+#define POWER9_PME_PM_PMC2_REWIND 784
+#define POWER9_PME_PM_INST_FROM_L2 785
+#define POWER9_PME_PM_MRK_NTF_FIN 786
+#define POWER9_PME_PM_ALL_SRQ_FULL 787
+#define POWER9_PME_PM_INST_DISP 788
+#define POWER9_PME_PM_LS3_ERAT_MISS_PREF 789
+#define POWER9_PME_PM_STOP_FETCH_PENDING_CYC 790
+#define POWER9_PME_PM_L1_DCACHE_RELOAD_VALID 791
+#define POWER9_PME_PM_L3_P0_LCO_NO_DATA 792
+#define POWER9_PME_PM_LSU3_VECTOR_LD_FIN 793
+#define POWER9_PME_PM_MRK_DPTEG_FROM_L3_NO_CONFLICT 794
+#define POWER9_PME_PM_MRK_FXU_FIN 795
+#define POWER9_PME_PM_LS3_UNALIGNED_ST 796
+#define POWER9_PME_PM_DPTEG_FROM_MEMORY 797
+#define POWER9_PME_PM_RUN_CYC_ST_MODE 798
+#define POWER9_PME_PM_PMC4_OVERFLOW 799
+#define POWER9_PME_PM_THRESH_EXC_256 800
+#define POWER9_PME_PM_MRK_DATA_FROM_L3_1_ECO_MOD_CYC 801
+#define POWER9_PME_PM_LSU0_LRQ_S0_VALID_CYC 802
+#define POWER9_PME_PM_INST_FROM_L2MISS 803
+#define POWER9_PME_PM_MRK_L2_TM_ST_ABORT_SISTER 804
+#define POWER9_PME_PM_L2_ST 805
+#define POWER9_PME_PM_RADIX_PWC_MISS 806
+#define POWER9_PME_PM_MRK_ST_L2DISP_TO_CMPL_CYC 807
+#define POWER9_PME_PM_LSU1_LDMX_FIN 808
+#define POWER9_PME_PM_L3_P2_LCO_RTY 809
+#define POWER9_PME_PM_MRK_DATA_FROM_DL2L3_SHR 810
+#define POWER9_PME_PM_L2_GRP_GUESS_CORRECT 811
+#define POWER9_PME_PM_LSU0_1_LRQF_FULL_CYC 812
+#define POWER9_PME_PM_DATA_GRP_PUMP_MPRED 813
+#define POWER9_PME_PM_LSU3_ERAT_HIT 814
+#define POWER9_PME_PM_FORCED_NOP 815
+#define POWER9_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST 816
+#define POWER9_PME_PM_CMPLU_STALL_LARX 817
+#define POWER9_PME_PM_MRK_DPTEG_FROM_RL4 818
+#define POWER9_PME_PM_MRK_DATA_FROM_L2 819
+#define POWER9_PME_PM_TM_FAIL_CONF_NON_TM 820
+#define POWER9_PME_PM_DPTEG_FROM_RL2L3_SHR 821
+#define POWER9_PME_PM_DARQ_4_6_ENTRIES 822
+#define POWER9_PME_PM_L2_SYS_PUMP 823
+#define POWER9_PME_PM_IOPS_CMPL 824
+#define POWER9_PME_PM_LSU_FLUSH_LHS 825
+#define POWER9_PME_PM_DATA_FROM_L3_1_SHR 826
+#define POWER9_PME_PM_NTC_FIN 827
+#define POWER9_PME_PM_LS2_DC_COLLISIONS 828
+#define POWER9_PME_PM_FMA_CMPL 829
+#define POWER9_PME_PM_IPTEG_FROM_MEMORY 830
+#define POWER9_PME_PM_TM_NON_FAV_TBEGIN 831
+#define POWER9_PME_PM_PMC1_REWIND 832
+#define POWER9_PME_PM_ISU2_ISS_HOLD_ALL 833
+#define POWER9_PME_PM_MRK_DATA_FROM_DL2L3_MOD_CYC 834
+#define POWER9_PME_PM_PTESYNC 835
+#define POWER9_PME_PM_ISIDE_DISP_FAIL_OTHER 836
+#define POWER9_PME_PM_L2_IC_INV 837
+#define POWER9_PME_PM_DPTEG_FROM_L3 838
+#define POWER9_PME_PM_RADIX_PWC_L2_HIT 839
+#define POWER9_PME_PM_DC_PREF_HW_ALLOC 840
+#define POWER9_PME_PM_LSU0_VECTOR_LD_FIN 841
+#define POWER9_PME_PM_1PLUS_PPC_DISP 842
+#define POWER9_PME_PM_RADIX_PWC_L3_PTE_FROM_L2 843
+#define POWER9_PME_PM_DATA_FROM_L2MISS 844
+#define POWER9_PME_PM_MRK_FAB_RSP_RD_T_INTV 845
+#define POWER9_PME_PM_NTC_ISSUE_HELD_ARB 846
+#define POWER9_PME_PM_LSU2_L1_CAM_CANCEL 847
+#define POWER9_PME_PM_L3_GRP_GUESS_WRONG_HIGH 848
+#define POWER9_PME_PM_DATA_FROM_L3_NO_CONFLICT 849
+#define POWER9_PME_PM_SUSPENDED 850
+#define POWER9_PME_PM_L3_SYS_GUESS_WRONG 851
+#define POWER9_PME_PM_L3_L2_CO_HIT 852
+#define POWER9_PME_PM_LSU0_TM_L1_HIT 853
+#define POWER9_PME_PM_BR_MPRED_PCACHE 854
+#define POWER9_PME_PM_STCX_FAIL 855
+#define POWER9_PME_PM_LSU_FLUSH_NEXT 856
+#define POWER9_PME_PM_DSIDE_MRU_TOUCH 857
+#define POWER9_PME_PM_SN_MISS 858
+#define POWER9_PME_PM_BR_PRED_TAKEN_CMPL 859
+#define POWER9_PME_PM_L3_P0_SYS_PUMP 860
+#define POWER9_PME_PM_L3_HIT 861
+#define POWER9_PME_PM_MRK_DFU_FIN 862
+#define POWER9_PME_PM_CMPLU_STALL_NESTED_TEND 863
+#define POWER9_PME_PM_INST_FROM_L1 864
+#define POWER9_PME_PM_IC_DEMAND_REQ 865
+#define POWER9_PME_PM_BRU_FIN 866
+#define POWER9_PME_PM_L1_ICACHE_RELOADED_ALL 867
+#define POWER9_PME_PM_IERAT_RELOAD_16M 868
+#define POWER9_PME_PM_DATA_FROM_L2MISS_MOD 869
+#define POWER9_PME_PM_LSU0_ERAT_HIT 870
+#define POWER9_PME_PM_L3_PF0_BUSY 871
+#define POWER9_PME_PM_MRK_DPTEG_FROM_LL4 872
+#define POWER9_PME_PM_LSU3_SET_MPRED 873
+#define POWER9_PME_PM_TM_CAM_OVERFLOW 874
+#define POWER9_PME_PM_SYNC_MRK_FX_DIVIDE 875
+#define POWER9_PME_PM_IPTEG_FROM_L2_1_SHR 876
+#define POWER9_PME_PM_MRK_LD_MISS_L1 877
+#define POWER9_PME_PM_MRK_FAB_RSP_DCLAIM 878
+#define POWER9_PME_PM_IPTEG_FROM_L3_DISP_CONFLICT 879
+#define POWER9_PME_PM_NON_FMA_FLOP_CMPL 880
+#define POWER9_PME_PM_MRK_DATA_FROM_L2MISS 881
+#define POWER9_PME_PM_L2_SYS_GUESS_WRONG 882
+#define POWER9_PME_PM_THRESH_EXC_2048 883
+#define POWER9_PME_PM_INST_FROM_LL4 884
+#define POWER9_PME_PM_DATA_FROM_RL2L3_SHR 885
+#define POWER9_PME_PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST 886
+#define POWER9_PME_PM_LSU_FLUSH_WRK_ARND 887
+#define POWER9_PME_PM_L3_PF_HIT_L3 888
+#define POWER9_PME_PM_RD_FORMING_SC 889
+#define POWER9_PME_PM_MRK_DATA_FROM_L2_1_MOD_CYC 890
+#define POWER9_PME_PM_IPTEG_FROM_DL4 891
+#define POWER9_PME_PM_CMPLU_STALL_STORE_FINISH 892
+#define POWER9_PME_PM_IPTEG_FROM_LL4 893
+#define POWER9_PME_PM_1FLOP_CMPL 894
+#define POWER9_PME_PM_L2_GRP_GUESS_WRONG 895
+#define POWER9_PME_PM_TM_FAV_TBEGIN 896
+#define POWER9_PME_PM_INST_FROM_L2_NO_CONFLICT 897
+#define POWER9_PME_PM_2FLOP_CMPL 898
+#define POWER9_PME_PM_LS2_TM_DISALLOW 899
+#define POWER9_PME_PM_L2_LD_DISP 900
+#define POWER9_PME_PM_CMPLU_STALL_LHS 901
+#define POWER9_PME_PM_TLB_HIT 902
+#define POWER9_PME_PM_HV_CYC 903
+#define POWER9_PME_PM_L2_RTY_LD 904
+#define POWER9_PME_PM_STCX_SUCCESS_CMPL 905
+#define POWER9_PME_PM_INST_PUMP_MPRED 906
+#define POWER9_PME_PM_LSU2_ERAT_HIT 907
+#define POWER9_PME_PM_INST_FROM_RL4 908
+#define POWER9_PME_PM_LD_L3MISS_PEND_CYC 909
+#define POWER9_PME_PM_L3_LAT_CI_MISS 910
+#define POWER9_PME_PM_MRK_FAB_RSP_RD_RTY 911
+#define POWER9_PME_PM_DTLB_MISS_16M 912
+#define POWER9_PME_PM_DPTEG_FROM_L2_1_MOD 913
+#define POWER9_PME_PM_MRK_DATA_FROM_RL2L3_SHR 914
+#define POWER9_PME_PM_MRK_LSU_FIN 915
+#define POWER9_PME_PM_LSU0_STORE_REJECT 916
+#define POWER9_PME_PM_CLB_HELD 917
+#define POWER9_PME_PM_LS2_ERAT_MISS_PREF 918
+static const pme_power_entry_t power9_pe[] = {
+[ POWER9_PME_PM_IERAT_RELOAD ] = { /* 0 */
+	.pme_name = "PM_IERAT_RELOAD",
+	.pme_code = 0x00000100F6,
+	.pme_short_desc = "Number of I-ERAT reloads",
+	.pme_long_desc = "Number of I-ERAT reloads",
+},
+[ POWER9_PME_PM_TM_OUTER_TEND ] = { /* 1 */
+	.pme_name = "PM_TM_OUTER_TEND",
+	.pme_code = 0x0000002894,
+	.pme_short_desc = "Completion time outer tend",
+	.pme_long_desc = "Completion time outer tend",
+},
+[ POWER9_PME_PM_IPTEG_FROM_L3 ] = { /* 2 */
+	.pme_name = "PM_IPTEG_FROM_L3",
+	.pme_code = 0x0000045042,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request",
+},
+[ POWER9_PME_PM_DPTEG_FROM_L3_1_MOD ] = { /* 3 */
+	.pme_name = "PM_DPTEG_FROM_L3_1_MOD",
+	.pme_code = 0x000002E044,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_PMC2_SAVED ] = { /* 4 */
+	.pme_name = "PM_PMC2_SAVED",
+	.pme_code = 0x0000010022,
+	.pme_short_desc = "PMC2 Rewind Value saved",
+	.pme_long_desc = "PMC2 Rewind Value saved",
+},
+[ POWER9_PME_PM_LSU_FLUSH_SAO ] = { /* 5 */
+	.pme_name = "PM_LSU_FLUSH_SAO",
+	.pme_code = 0x000000C0B8,
+	.pme_short_desc = "A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush",
+	.pme_long_desc = "A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush",
+},
+[ POWER9_PME_PM_CMPLU_STALL_DFU ] = { /* 6 */
+	.pme_name = "PM_CMPLU_STALL_DFU",
+	.pme_code = 0x000002D012,
+	.pme_short_desc = "Finish stall because the NTF instruction was issued to the Decimal Floating Point execution pipe and waiting to finish.",
+	.pme_long_desc = "Finish stall because the NTF instruction was issued to the Decimal Floating Point execution pipe and waiting to finish. Includes decimal floating point instructions + 128 bit binary floating point instructions. Not qualified by multicycle",
+},
+[ POWER9_PME_PM_MRK_LSU_FLUSH_RELAUNCH_MISS ] = { /* 7 */
+	.pme_name = "PM_MRK_LSU_FLUSH_RELAUNCH_MISS",
+	.pme_code = 0x000000D09C,
+	.pme_short_desc = "If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent",
+	.pme_long_desc = "If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent",
+},
+[ POWER9_PME_PM_SP_FLOP_CMPL ] = { /* 8 */
+	.pme_name = "PM_SP_FLOP_CMPL",
+	.pme_code = 0x000001505E,
+	.pme_short_desc = "Single-precision flop count",
+	.pme_long_desc = "Single-precision flop count",
+},
+[ POWER9_PME_PM_IC_RELOAD_PRIVATE ] = { /* 9 */
+	.pme_name = "PM_IC_RELOAD_PRIVATE",
+	.pme_code = 0x0000004894,
+	.pme_short_desc = "Reloading line was brought in private for a specific thread.",
+	.pme_long_desc = "Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight thrreads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was invalidat",
+},
+[ POWER9_PME_PM_RADIX_PWC_L2_PTE_FROM_L2 ] = { /* 10 */
+	.pme_name = "PM_RADIX_PWC_L2_PTE_FROM_L2",
+	.pme_code = 0x000001F058,
+	.pme_short_desc = "A Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 data cache.",
+	.pme_long_desc = "A Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 data cache. This implies that level 3 and level 4 PWC accesses were not necessary for this translation",
+},
+[ POWER9_PME_PM_INST_PUMP_CPRED ] = { /* 11 */
+	.pme_name = "PM_INST_PUMP_CPRED",
+	.pme_code = 0x0000014054,
+	.pme_short_desc = "Pump prediction correct.",
+	.pme_long_desc = "Pump prediction correct. Counts across all types of pumps for an instruction fetch",
+},
+[ POWER9_PME_PM_INST_FROM_L2_1_MOD ] = { /* 12 */
+	.pme_name = "PM_INST_FROM_L2_1_MOD",
+	.pme_code = 0x0000044046,
+	.pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_MRK_ST_CMPL ] = { /* 13 */
+	.pme_name = "PM_MRK_ST_CMPL",
+	.pme_code = 0x00000301E2,
+	.pme_short_desc = "Marked store completed and sent to nest",
+	.pme_long_desc = "Marked store completed and sent to nest",
+},
+[ POWER9_PME_PM_MRK_LSU_DERAT_MISS ] = { /* 14 */
+	.pme_name = "PM_MRK_LSU_DERAT_MISS",
+	.pme_code = 0x0000030162,
+	.pme_short_desc = "Marked derat reload (miss) for any page size",
+	.pme_long_desc = "Marked derat reload (miss) for any page size",
+},
+[ POWER9_PME_PM_L2_ST_DISP ] = { /* 15 */
+	.pme_name = "PM_L2_ST_DISP",
+	.pme_code = 0x000001689E,
+	.pme_short_desc = "All successful store dispatches",
+	.pme_long_desc = "All successful store dispatches",
+},
+[ POWER9_PME_PM_LSU0_FALSE_LHS ] = { /* 16 */
+	.pme_name = "PM_LSU0_FALSE_LHS",
+	.pme_code = 0x000000C0A0,
+	.pme_short_desc = "False LHS match detected",
+	.pme_long_desc = "False LHS match detected",
+},
+[ POWER9_PME_PM_L2_CASTOUT_MOD ] = { /* 17 */
+	.pme_name = "PM_L2_CASTOUT_MOD",
+	.pme_code = 0x0000016082,
+	.pme_short_desc = "L2 Castouts - Modified (M, Mu, Me)",
+	.pme_long_desc = "L2 Castouts - Modified (M, Mu, Me)",
+},
+[ POWER9_PME_PM_L2_RCST_DISP_FAIL_ADDR ] = { /* 18 */
+	.pme_name = "PM_L2_RCST_DISP_FAIL_ADDR",
+	.pme_code = 0x0000036884,
+	.pme_short_desc = "L2 RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ",
+	.pme_long_desc = "L2 RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ",
+},
+[ POWER9_PME_PM_MRK_INST_TIMEO ] = { /* 19 */
+	.pme_name = "PM_MRK_INST_TIMEO",
+	.pme_code = 0x0000040134,
+	.pme_short_desc = "marked Instruction finish timeout (instruction lost)",
+	.pme_long_desc = "marked Instruction finish timeout (instruction lost)",
+},
+[ POWER9_PME_PM_CMPLU_STALL_LOAD_FINISH ] = { /* 20 */
+	.pme_name = "PM_CMPLU_STALL_LOAD_FINISH",
+	.pme_code = 0x000004D014,
+	.pme_short_desc = "Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish",
+	.pme_long_desc = "Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish",
+},
+[ POWER9_PME_PM_INST_FROM_L2_1_SHR ] = { /* 21 */
+	.pme_name = "PM_INST_FROM_L2_1_SHR",
+	.pme_code = 0x0000034046,
+	.pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_LS1_DC_COLLISIONS ] = { /* 22 */
+	.pme_name = "PM_LS1_DC_COLLISIONS",
+	.pme_code = 0x000000D890,
+	.pme_short_desc = "Read-write data cache collisions",
+	.pme_long_desc = "Read-write data cache collisions",
+},
+[ POWER9_PME_PM_LSU2_FALSE_LHS ] = { /* 23 */
+	.pme_name = "PM_LSU2_FALSE_LHS",
+	.pme_code = 0x000000C0A4,
+	.pme_short_desc = "False LHS match detected",
+	.pme_long_desc = "False LHS match detected",
+},
+[ POWER9_PME_PM_MRK_ST_DRAIN_TO_L2DISP_CYC ] = { /* 24 */
+	.pme_name = "PM_MRK_ST_DRAIN_TO_L2DISP_CYC",
+	.pme_code = 0x000003F150,
+	.pme_short_desc = "cycles to drain st from core to L2",
+	.pme_long_desc = "cycles to drain st from core to L2",
+},
+[ POWER9_PME_PM_MRK_DTLB_MISS_16M ] = { /* 25 */
+	.pme_name = "PM_MRK_DTLB_MISS_16M",
+	.pme_code = 0x000004C15E,
+	.pme_short_desc = "Marked Data TLB Miss page size 16M",
+	.pme_long_desc = "Marked Data TLB Miss page size 16M",
+},
+[ POWER9_PME_PM_L2_GROUP_PUMP ] = { /* 26 */
+	.pme_name = "PM_L2_GROUP_PUMP",
+	.pme_code = 0x0000046888,
+	.pme_short_desc = "RC requests that were on Node Pump attempts",
+	.pme_long_desc = "RC requests that were on Node Pump attempts",
+},
+[ POWER9_PME_PM_LSU2_VECTOR_ST_FIN ] = { /* 27 */
+	.pme_name = "PM_LSU2_VECTOR_ST_FIN",
+	.pme_code = 0x000000C08C,
+	.pme_short_desc = "A vector store instruction finished.",
+	.pme_long_desc = "A vector store instruction finished. The ops considered in this category are stv*, stxv*, stxsi*x, stxsd, and stxssp",
+},
+[ POWER9_PME_PM_CMPLU_STALL_LSAQ_ARB ] = { /* 28 */
+	.pme_name = "PM_CMPLU_STALL_LSAQ_ARB",
+	.pme_code = 0x000004E016,
+	.pme_short_desc = "Finish stall because the NTF instruction was a load or store that was held in LSAQ because an older instruction from SRQ or LRQ won arbitration to the LSU pipe when this instruction tried to launch",
+	.pme_long_desc = "Finish stall because the NTF instruction was a load or store that was held in LSAQ because an older instruction from SRQ or LRQ won arbitration to the LSU pipe when this instruction tried to launch",
+},
+[ POWER9_PME_PM_L3_CO_LCO ] = { /* 29 */
+	.pme_name = "PM_L3_CO_LCO",
+	.pme_code = 0x00000360A4,
+	.pme_short_desc = "Total L3 castouts occurred on LCO",
+	.pme_long_desc = "Total L3 castouts occurred on LCO",
+},
+[ POWER9_PME_PM_INST_GRP_PUMP_CPRED ] = { /* 30 */
+	.pme_name = "PM_INST_GRP_PUMP_CPRED",
+	.pme_code = 0x000002C05C,
+	.pme_short_desc = "Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch (demand only)",
+	.pme_long_desc = "Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch (demand only)",
+},
+[ POWER9_PME_PM_THRD_PRIO_4_5_CYC ] = { /* 31 */
+	.pme_name = "PM_THRD_PRIO_4_5_CYC",
+	.pme_code = 0x0000005080,
+	.pme_short_desc = "Cycles thread running at priority level 4 or 5",
+	.pme_long_desc = "Cycles thread running at priority level 4 or 5",
+},
+[ POWER9_PME_PM_BR_PRED_TA ] = { /* 32 */
+	.pme_name = "PM_BR_PRED_TA",
+	.pme_code = 0x00000040B4,
+	.pme_short_desc = "Conditional Branch Completed that had its target address predicted.",
+	.pme_long_desc = "Conditional Branch Completed that had its target address predicted. Only XL-form branches set this event. This equal the sum of CCACHE, LSTACK, and PCACHE",
+},
+[ POWER9_PME_PM_ICT_NOSLOT_BR_MPRED_ICMISS ] = { /* 33 */
+	.pme_name = "PM_ICT_NOSLOT_BR_MPRED_ICMISS",
+	.pme_code = 0x0000034058,
+	.pme_short_desc = "Ict empty for this thread due to Icache Miss and branch mispred",
+	.pme_long_desc = "Ict empty for this thread due to Icache Miss and branch mispred",
+},
+[ POWER9_PME_PM_IPTEG_FROM_L3_NO_CONFLICT ] = { /* 34 */
+	.pme_name = "PM_IPTEG_FROM_L3_NO_CONFLICT",
+	.pme_code = 0x0000015044,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request",
+},
+[ POWER9_PME_PM_CMPLU_STALL_FXU ] = { /* 35 */
+	.pme_name = "PM_CMPLU_STALL_FXU",
+	.pme_code = 0x000002D016,
+	.pme_short_desc = "Finish stall due to a scalar fixed point or CR instruction in the execution pipeline.",
+	.pme_long_desc = "Finish stall due to a scalar fixed point or CR instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes",
+},
+[ POWER9_PME_PM_VSU_FSQRT_FDIV ] = { /* 36 */
+	.pme_name = "PM_VSU_FSQRT_FDIV",
+	.pme_code = 0x000004D04E,
+	.pme_short_desc = "four flops operation (fdiv,fsqrt) Scalar Instructions only",
+	.pme_long_desc = "four flops operation (fdiv,fsqrt) Scalar Instructions only",
+},
+[ POWER9_PME_PM_EXT_INT ] = { /* 37 */
+	.pme_name = "PM_EXT_INT",
+	.pme_code = 0x00000200F8,
+	.pme_short_desc = "external interrupt",
+	.pme_long_desc = "external interrupt",
+},
+[ POWER9_PME_PM_MRK_LD_MISS_EXPOSED_CYC ] = { /* 38 */
+	.pme_name = "PM_MRK_LD_MISS_EXPOSED_CYC",
+	.pme_code = 0x000001013E,
+	.pme_short_desc = "Marked Load exposed Miss (use edge detect to count #)",
+	.pme_long_desc = "Marked Load exposed Miss (use edge detect to count #)",
+},
+[ POWER9_PME_PM_S2Q_FULL ] = { /* 39 */
+	.pme_name = "PM_S2Q_FULL",
+	.pme_code = 0x000000E080,
+	.pme_short_desc = "Cycles during which the S2Q is full",
+	.pme_long_desc = "Cycles during which the S2Q is full",
+},
+[ POWER9_PME_PM_RUN_CYC_SMT2_MODE ] = { /* 40 */
+	.pme_name = "PM_RUN_CYC_SMT2_MODE",
+	.pme_code = 0x000003006C,
+	.pme_short_desc = "Cycles in which this thread's run latch is set and the core is in SMT2 mode",
+	.pme_long_desc = "Cycles in which this thread's run latch is set and the core is in SMT2 mode",
+},
+[ POWER9_PME_PM_DECODE_LANES_NOT_AVAIL ] = { /* 41 */
+	.pme_name = "PM_DECODE_LANES_NOT_AVAIL",
+	.pme_code = 0x0000005884,
+	.pme_short_desc = "Decode has something to transmit but dispatch lanes are not available",
+	.pme_long_desc = "Decode has something to transmit but dispatch lanes are not available",
+},
+[ POWER9_PME_PM_TM_FAIL_TLBIE ] = { /* 42 */
+	.pme_name = "PM_TM_FAIL_TLBIE",
+	.pme_code = 0x000000E0AC,
+	.pme_short_desc = "Transaction failed because there was a TLBIE hit in the bloom filter",
+	.pme_long_desc = "Transaction failed because there was a TLBIE hit in the bloom filter",
+},
+[ POWER9_PME_PM_DISP_CLB_HELD_BAL ] = { /* 43 */
+	.pme_name = "PM_DISP_CLB_HELD_BAL",
+	.pme_code = 0x000000288C,
+	.pme_short_desc = "Dispatch/CLB Hold: Balance Flush",
+	.pme_long_desc = "Dispatch/CLB Hold: Balance Flush",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L3MISS_CYC ] = { /* 44 */
+	.pme_name = "PM_MRK_DATA_FROM_L3MISS_CYC",
+	.pme_code = 0x000001415E,
+	.pme_short_desc = "Duration in cycles to reload from a localtion other than the local core's L3 due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload from a localtion other than the local core's L3 due to a marked load",
+},
+[ POWER9_PME_PM_MRK_ST_FWD ] = { /* 45 */
+	.pme_name = "PM_MRK_ST_FWD",
+	.pme_code = 0x000003012C,
+	.pme_short_desc = "Marked st forwards",
+	.pme_long_desc = "Marked st forwards",
+},
+[ POWER9_PME_PM_FXU_FIN ] = { /* 46 */
+	.pme_name = "PM_FXU_FIN",
+	.pme_code = 0x0000040004,
+	.pme_short_desc = "The fixed point unit Unit finished an instruction.",
+	.pme_long_desc = "The fixed point unit Unit finished an instruction. Instructions that finish may not necessary complete.",
+},
+[ POWER9_PME_PM_SYNC_MRK_BR_MPRED ] = { /* 47 */
+	.pme_name = "PM_SYNC_MRK_BR_MPRED",
+	.pme_code = 0x000001515C,
+	.pme_short_desc = "Marked Branch mispredict that can cause a synchronous interrupt",
+	.pme_long_desc = "Marked Branch mispredict that can cause a synchronous interrupt",
+},
+[ POWER9_PME_PM_CMPLU_STALL_STORE_FIN_ARB ] = { /* 48 */
+	.pme_name = "PM_CMPLU_STALL_STORE_FIN_ARB",
+	.pme_code = 0x0000030014,
+	.pme_short_desc = "Finish stall because the NTF instruction was a store waiting for a slot in the store finish pipe.",
+	.pme_long_desc = "Finish stall because the NTF instruction was a store waiting for a slot in the store finish pipe. This means the instruction is ready to finish but there are instructions ahead of it, using the finish pipe",
+},
+[ POWER9_PME_PM_DSLB_MISS ] = { /* 49 */
+	.pme_name = "PM_DSLB_MISS",
+	.pme_code = 0x000000D0A8,
+	.pme_short_desc = "Data SLB Miss - Total of all segment sizes",
+	.pme_long_desc = "Data SLB Miss - Total of all segment sizes",
+},
+[ POWER9_PME_PM_L3_MISS ] = { /* 50 */
+	.pme_name = "PM_L3_MISS",
+	.pme_code = 0x00000168A4,
+	.pme_short_desc = "L3 Misses",
+	.pme_long_desc = "L3 Misses",
+},
+[ POWER9_PME_PM_DUMMY2_REMOVE_ME ] = { /* 51 */
+	.pme_name = "PM_DUMMY2_REMOVE_ME",
+	.pme_code = 0x0000040064,
+	.pme_short_desc = "Space holder for LS_PC_RELOAD_RA",
+	.pme_long_desc = "Space holder for LS_PC_RELOAD_RA",
+},
+[ POWER9_PME_PM_MRK_DERAT_MISS_1G ] = { /* 52 */
+	.pme_name = "PM_MRK_DERAT_MISS_1G",
+	.pme_code = 0x000003D152,
+	.pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 1G.",
+	.pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 1G. Implies radix translation",
+},
+[ POWER9_PME_PM_MATH_FLOP_CMPL ] = { /* 53 */
+	.pme_name = "PM_MATH_FLOP_CMPL",
+	.pme_code = 0x0000010066,
+	.pme_short_desc = "",
+	.pme_long_desc = "",
+},
+[ POWER9_PME_PM_L2_INST ] = { /* 54 */
+	.pme_name = "PM_L2_INST",
+	.pme_code = 0x000003609E,
+	.pme_short_desc = "All successful I-side dispatches for this thread (excludes i_l2mru_tch reqs)",
+	.pme_long_desc = "All successful I-side dispatches for this thread (excludes i_l2mru_tch reqs)",
+},
+[ POWER9_PME_PM_FLUSH_DISP ] = { /* 55 */
+	.pme_name = "PM_FLUSH_DISP",
+	.pme_code = 0x0000002880,
+	.pme_short_desc = "Dispatch flush",
+	.pme_long_desc = "Dispatch flush",
+},
+[ POWER9_PME_PM_DISP_HELD_ISSQ_FULL ] = { /* 56 */
+	.pme_name = "PM_DISP_HELD_ISSQ_FULL",
+	.pme_code = 0x0000020006,
+	.pme_short_desc = "Dispatch held due to Issue q full.",
+	.pme_long_desc = "Dispatch held due to Issue q full. Includes issue queue and branch queue",
+},
+[ POWER9_PME_PM_MEM_READ ] = { /* 57 */
+	.pme_name = "PM_MEM_READ",
+	.pme_code = 0x0000010056,
+	.pme_short_desc = "Reads from Memory from this thread (includes data/inst/xlate/l1prefetch/inst prefetch).",
+	.pme_long_desc = "Reads from Memory from this thread (includes data/inst/xlate/l1prefetch/inst prefetch). Includes L4",
+},
+[ POWER9_PME_PM_DATA_PUMP_MPRED ] = { /* 58 */
+	.pme_name = "PM_DATA_PUMP_MPRED",
+	.pme_code = 0x000004C052,
+	.pme_short_desc = "Pump misprediction.",
+	.pme_long_desc = "Pump misprediction. Counts across all types of pumps for a demand load",
+},
+[ POWER9_PME_PM_DATA_CHIP_PUMP_CPRED ] = { /* 59 */
+	.pme_name = "PM_DATA_CHIP_PUMP_CPRED",
+	.pme_code = 0x000001C050,
+	.pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load",
+	.pme_long_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_DMEM ] = { /* 60 */
+	.pme_name = "PM_MRK_DATA_FROM_DMEM",
+	.pme_code = 0x000003D14C,
+	.pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load",
+},
+[ POWER9_PME_PM_CMPLU_STALL_LSU ] = { /* 61 */
+	.pme_name = "PM_CMPLU_STALL_LSU",
+	.pme_code = 0x000002C010,
+	.pme_short_desc = "Completion stall by LSU instruction",
+	.pme_long_desc = "Completion stall by LSU instruction",
+},
+[ POWER9_PME_PM_DATA_FROM_L3_1_MOD ] = { /* 62 */
+	.pme_name = "PM_DATA_FROM_L3_1_MOD",
+	.pme_code = 0x000002C044,
+	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a demand load",
+},
+[ POWER9_PME_PM_MRK_DERAT_MISS_16M ] = { /* 63 */
+	.pme_name = "PM_MRK_DERAT_MISS_16M",
+	.pme_code = 0x000003D154,
+	.pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 16M",
+	.pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 16M",
+},
+[ POWER9_PME_PM_TM_TRANS_RUN_CYC ] = { /* 64 */
+	.pme_name = "PM_TM_TRANS_RUN_CYC",
+	.pme_code = 0x0000010060,
+	.pme_short_desc = "run cycles in transactional state",
+	.pme_long_desc = "run cycles in transactional state",
+},
+[ POWER9_PME_PM_THRD_ALL_RUN_CYC ] = { /* 65 */
+	.pme_name = "PM_THRD_ALL_RUN_CYC",
+	.pme_code = 0x0000020008,
+	.pme_short_desc = "Cycles in which all the threads have the run latch set",
+	.pme_long_desc = "Cycles in which all the threads have the run latch set",
+},
+[ POWER9_PME_PM_DATA_FROM_DL2L3_MOD ] = { /* 66 */
+	.pme_name = "PM_DATA_FROM_DL2L3_MOD",
+	.pme_code = 0x000004C048,
+	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
+},
+[ POWER9_PME_PM_MRK_BR_MPRED_CMPL ] = { /* 67 */
+	.pme_name = "PM_MRK_BR_MPRED_CMPL",
+	.pme_code = 0x00000301E4,
+	.pme_short_desc = "Marked Branch Mispredicted",
+	.pme_long_desc = "Marked Branch Mispredicted",
+},
+[ POWER9_PME_PM_ICT_NOSLOT_DISP_HELD_ISSQ ] = { /* 68 */
+	.pme_name = "PM_ICT_NOSLOT_DISP_HELD_ISSQ",
+	.pme_code = 0x000002D01E,
+	.pme_short_desc = "Ict empty for this thread due to dispatch hold on this thread due to Issue q full, BRQ full, XVCF Full, Count cache, Link, Tar full",
+	.pme_long_desc = "Ict empty for this thread due to dispatch hold on this thread due to Issue q full, BRQ full, XVCF Full, Count cache, Link, Tar full",
+},
+[ POWER9_PME_PM_MRK_INST ] = { /* 69 */
+	.pme_name = "PM_MRK_INST",
+	.pme_code = 0x0000024058,
+	.pme_short_desc = "An instruction was marked.",
+	.pme_long_desc = "An instruction was marked. Includes both Random Instruction Sampling (RIS) at decode time and Random Event Samping (RES) at the time the configured event happens",
+},
+[ POWER9_PME_PM_TABLEWALK_CYC_PREF ] = { /* 70 */
+	.pme_name = "PM_TABLEWALK_CYC_PREF",
+	.pme_code = 0x000000F884,
+	.pme_short_desc = "tablewalk qualified for pte prefetches",
+	.pme_long_desc = "tablewalk qualified for pte prefetches",
+},
+[ POWER9_PME_PM_LSU1_ERAT_HIT ] = { /* 71 */
+	.pme_name = "PM_LSU1_ERAT_HIT",
+	.pme_code = 0x000000E88C,
+	.pme_short_desc = "Primary ERAT hit.",
+	.pme_long_desc = "Primary ERAT hit. There is no secondary ERAT",
+},
+[ POWER9_PME_PM_NTC_ISSUE_HELD_OTHER ] = { /* 72 */
+	.pme_name = "PM_NTC_ISSUE_HELD_OTHER",
+	.pme_code = 0x000003D05A,
+	.pme_short_desc = "The NTC instruction is being held at dispatch during regular pipeline cycles, or because the VSU is busy with multi-cycle instructions, or because of a write-back collision with VSU",
+	.pme_long_desc = "The NTC instruction is being held at dispatch during regular pipeline cycles, or because the VSU is busy with multi-cycle instructions, or because of a write-back collision with VSU",
+},
+[ POWER9_PME_PM_CMPLU_STALL_LSU_FLUSH_NEXT ] = { /* 73 */
+	.pme_name = "PM_CMPLU_STALL_LSU_FLUSH_NEXT",
+	.pme_code = 0x000002E01A,
+	.pme_short_desc = "Completion stall of one cycle because the LSU requested to flush the next iop in the sequence.",
+	.pme_long_desc = "Completion stall of one cycle because the LSU requested to flush the next iop in the sequence. It takes 1 cycle for the ISU to process this request before the LSU instruction is allowed to complete",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_L2 ] = { /* 74 */
+	.pme_name = "PM_MRK_DPTEG_FROM_L2",
+	.pme_code = 0x000001F142,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_LS1_TM_DISALLOW ] = { /* 75 */
+	.pme_name = "PM_LS1_TM_DISALLOW",
+	.pme_code = 0x000000E8B4,
+	.pme_short_desc = "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it",
+	.pme_long_desc = "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it",
+},
+[ POWER9_PME_PM_INST_FROM_L2_DISP_CONFLICT_LDHITST ] = { /* 76 */
+	.pme_name = "PM_INST_FROM_L2_DISP_CONFLICT_LDHITST",
+	.pme_code = 0x0000034040,
+	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_BR_PRED_PCACHE ] = { /* 77 */
+	.pme_name = "PM_BR_PRED_PCACHE",
+	.pme_code = 0x00000048A0,
+	.pme_short_desc = "Conditional branch completed that used pattern cache prediction",
+	.pme_long_desc = "Conditional branch completed that used pattern cache prediction",
+},
+[ POWER9_PME_PM_MRK_BACK_BR_CMPL ] = { /* 78 */
+	.pme_name = "PM_MRK_BACK_BR_CMPL",
+	.pme_code = 0x000003515E,
+	.pme_short_desc = "Marked branch instruction completed with a target address less than current instruction address",
+	.pme_long_desc = "Marked branch instruction completed with a target address less than current instruction address",
+},
+[ POWER9_PME_PM_RD_CLEARING_SC ] = { /* 79 */
+	.pme_name = "PM_RD_CLEARING_SC",
+	.pme_code = 0x00000468A6,
+	.pme_short_desc = "rd clearing sc",
+	.pme_long_desc = "rd clearing sc",
+},
+[ POWER9_PME_PM_PMC1_OVERFLOW ] = { /* 80 */
+	.pme_name = "PM_PMC1_OVERFLOW",
+	.pme_code = 0x0000020010,
+	.pme_short_desc = "Overflow from counter 1",
+	.pme_long_desc = "Overflow from counter 1",
+},
+[ POWER9_PME_PM_L2_RTY_ST ] = { /* 81 */
+	.pme_name = "PM_L2_RTY_ST",
+	.pme_code = 0x000004689E,
+	.pme_short_desc = "RC retries on PB for any store from core",
+	.pme_long_desc = "RC retries on PB for any store from core",
+},
+[ POWER9_PME_PM_IPTEG_FROM_L2_NO_CONFLICT ] = { /* 82 */
+	.pme_name = "PM_IPTEG_FROM_L2_NO_CONFLICT",
+	.pme_code = 0x0000015040,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction side request",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction side request",
+},
+[ POWER9_PME_PM_LSU1_FALSE_LHS ] = { /* 83 */
+	.pme_name = "PM_LSU1_FALSE_LHS",
+	.pme_code = 0x000000C8A0,
+	.pme_short_desc = "False LHS match detected",
+	.pme_long_desc = "False LHS match detected",
+},
+[ POWER9_PME_PM_LSU0_VECTOR_ST_FIN ] = { /* 84 */
+	.pme_name = "PM_LSU0_VECTOR_ST_FIN",
+	.pme_code = 0x000000C088,
+	.pme_short_desc = "A vector store instruction finished.",
+	.pme_long_desc = "A vector store instruction finished. The ops considered in this category are stv*, stxv*, stxsi*x, stxsd, and stxssp",
+},
+[ POWER9_PME_PM_MEM_LOC_THRESH_LSU_HIGH ] = { /* 85 */
+	.pme_name = "PM_MEM_LOC_THRESH_LSU_HIGH",
+	.pme_code = 0x0000040056,
+	.pme_short_desc = "Local memory above threshold for LSU medium",
+	.pme_long_desc = "Local memory above threshold for LSU medium",
+},
+[ POWER9_PME_PM_LS2_UNALIGNED_LD ] = { /* 86 */
+	.pme_name = "PM_LS2_UNALIGNED_LD",
+	.pme_code = 0x000000C098,
+	.pme_short_desc = "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size.",
+	.pme_long_desc = "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty",
+},
+[ POWER9_PME_PM_BR_TAKEN_CMPL ] = { /* 87 */
+	.pme_name = "PM_BR_TAKEN_CMPL",
+	.pme_code = 0x00000200FA,
+	.pme_short_desc = "New event for Branch Taken",
+	.pme_long_desc = "New event for Branch Taken",
+},
+[ POWER9_PME_PM_DATA_SYS_PUMP_MPRED ] = { /* 88 */
+	.pme_name = "PM_DATA_SYS_PUMP_MPRED",
+	.pme_code = 0x000003C052,
+	.pme_short_desc = "Final Pump Scope (system) mispredicted.",
+	.pme_long_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for a demand load",
+},
+[ POWER9_PME_PM_ISQ_36_44_ENTRIES ] = { /* 89 */
+	.pme_name = "PM_ISQ_36_44_ENTRIES",
+	.pme_code = 0x000004000A,
+	.pme_short_desc = "Cycles in which 36 or more Issue Queue entries are in use.",
+	.pme_long_desc = "Cycles in which 36 or more Issue Queue entries are in use. This is a shared event, not per thread. There are 44 issue queue entries across 4 slices in the whole core",
+},
+[ POWER9_PME_PM_LSU1_VECTOR_LD_FIN ] = { /* 90 */
+	.pme_name = "PM_LSU1_VECTOR_LD_FIN",
+	.pme_code = 0x000000C880,
+	.pme_short_desc = "A vector load instruction finished.",
+	.pme_long_desc = "A vector load instruction finished. The ops considered in this category are lxv*, lvx*, lve*, lxsi*zx, lxvwsx, lxsd, lxssp, lxvl, lxvll, lxvb16x, lxvh8x, lxv, lxvx",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER ] = { /* 91 */
+	.pme_name = "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER",
+	.pme_code = 0x000002C124,
+	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load",
+},
+[ POWER9_PME_PM_ICT_NOSLOT_IC_MISS ] = { /* 92 */
+	.pme_name = "PM_ICT_NOSLOT_IC_MISS",
+	.pme_code = 0x000002D01A,
+	.pme_short_desc = "Ict empty for this thread due to Icache Miss",
+	.pme_long_desc = "Ict empty for this thread due to Icache Miss",
+},
+[ POWER9_PME_PM_LSU3_TM_L1_HIT ] = { /* 93 */
+	.pme_name = "PM_LSU3_TM_L1_HIT",
+	.pme_code = 0x000000E898,
+	.pme_short_desc = "Load tm hit in L1",
+	.pme_long_desc = "Load tm hit in L1",
+},
+[ POWER9_PME_PM_MRK_INST_DISP ] = { /* 94 */
+	.pme_name = "PM_MRK_INST_DISP",
+	.pme_code = 0x00000101E0,
+	.pme_short_desc = "The thread has dispatched a randomly sampled marked instruction",
+	.pme_long_desc = "The thread has dispatched a randomly sampled marked instruction",
+},
+[ POWER9_PME_PM_VECTOR_FLOP_CMPL ] = { /* 95 */
+	.pme_name = "PM_VECTOR_FLOP_CMPL",
+	.pme_code = 0x000004D058,
+	.pme_short_desc = "Vector flop instruction completed",
+	.pme_long_desc = "Vector flop instruction completed",
+},
+[ POWER9_PME_PM_FXU_IDLE ] = { /* 96 */
+	.pme_name = "PM_FXU_IDLE",
+	.pme_code = 0x0000024052,
+	.pme_short_desc = "Cycles in which FXU0, FXU1, FXU2, and FXU3 are all idle",
+	.pme_long_desc = "Cycles in which FXU0, FXU1, FXU2, and FXU3 are all idle",
+},
+[ POWER9_PME_PM_INST_CMPL ] = { /* 97 */
+	.pme_name = "PM_INST_CMPL",
+	.pme_code = 0x0000010002,
+	.pme_short_desc = "# PPC instructions completed",
+	.pme_long_desc = "# PPC instructions completed",
+},
+[ POWER9_PME_PM_EAT_FORCE_MISPRED ] = { /* 98 */
+	.pme_name = "PM_EAT_FORCE_MISPRED",
+	.pme_code = 0x00000050A8,
+	.pme_short_desc = "XL-form branch was mispredicted due to the predicted target address missing from EAT.",
+	.pme_long_desc = "XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is issued",
+},
+[ POWER9_PME_PM_CMPLU_STALL_LRQ_FULL ] = { /* 99 */
+	.pme_name = "PM_CMPLU_STALL_LRQ_FULL",
+	.pme_code = 0x000002D014,
+	.pme_short_desc = "Finish stall because the NTF instruction was a load that was held in LSAQ because the LRQ was full",
+	.pme_long_desc = "Finish stall because the NTF instruction was a load that was held in LSAQ because the LRQ was full",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_DL2L3_MOD ] = { /* 100 */
+	.pme_name = "PM_MRK_DATA_FROM_DL2L3_MOD",
+	.pme_code = 0x000003D14E,
+	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
+},
+[ POWER9_PME_PM_BACK_BR_CMPL ] = { /* 101 */
+	.pme_name = "PM_BACK_BR_CMPL",
+	.pme_code = 0x000002505E,
+	.pme_short_desc = "Branch instruction completed with a target address less than current instruction address",
+	.pme_long_desc = "Branch instruction completed with a target address less than current instruction address",
+},
+[ POWER9_PME_PM_NEST_REF_CLK ] = { /* 102 */
+	.pme_name = "PM_NEST_REF_CLK",
+	.pme_code = 0x000003006E,
+	.pme_short_desc = "Multiply by 4 to obtain the number of PB cycles",
+	.pme_long_desc = "Multiply by 4 to obtain the number of PB cycles",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_RL2L3_SHR ] = { /* 103 */
+	.pme_name = "PM_MRK_DPTEG_FROM_RL2L3_SHR",
+	.pme_code = 0x000001F14A,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_RC_USAGE ] = { /* 104 */
+	.pme_name = "PM_RC_USAGE",
+	.pme_code = 0x000001688E,
+	.pme_short_desc = " continuous 16 cycle(2to1) window where this signals rotates thru sampling each machine",
+	.pme_long_desc = " continuous 16 cycle(2to1) window where this signals rotates thru sampling each machine",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_L3_1_ECO_MOD ] = { /* 105 */
+	.pme_name = "PM_MRK_DPTEG_FROM_L3_1_ECO_MOD",
+	.pme_code = 0x000004F144,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_BR_CMPL ] = { /* 106 */
+	.pme_name = "PM_BR_CMPL",
+	.pme_code = 0x0000010012,
+	.pme_short_desc = "Branch Instruction completed",
+	.pme_long_desc = "Branch Instruction completed",
+},
+[ POWER9_PME_PM_INST_FROM_RL2L3_MOD ] = { /* 107 */
+	.pme_name = "PM_INST_FROM_RL2L3_MOD",
+	.pme_code = 0x0000024046,
+	.pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_SHL_CREATED ] = { /* 108 */
+	.pme_name = "PM_SHL_CREATED",
+	.pme_code = 0x000000508C,
+	.pme_short_desc = "Store-Hit-Load Table Entry Created",
+	.pme_long_desc = "Store-Hit-Load Table Entry Created",
+},
+[ POWER9_PME_PM_CMPLU_STALL_PASTE ] = { /* 109 */
+	.pme_name = "PM_CMPLU_STALL_PASTE",
+	.pme_code = 0x000002C016,
+	.pme_short_desc = "Finish stall because the NTF instruction was a paste waiting for response from L2",
+	.pme_long_desc = "Finish stall because the NTF instruction was a paste waiting for response from L2",
+},
+[ POWER9_PME_PM_LSU3_LDMX_FIN ] = { /* 110 */
+	.pme_name = "PM_LSU3_LDMX_FIN",
+	.pme_code = 0x000000D88C,
+	.pme_short_desc = " New P9 instruction LDMX.",
+	.pme_long_desc = " New P9 instruction LDMX.",
+},
+[ POWER9_PME_PM_SN_USAGE ] = { /* 111 */
+	.pme_name = "PM_SN_USAGE",
+	.pme_code = 0x000003688E,
+	.pme_short_desc = " continuous 16 cycle(2to1) window where this signals rotates thru sampling each machine",
+	.pme_long_desc = " continuous 16 cycle(2to1) window where this signals rotates thru sampling each machine",
+},
+[ POWER9_PME_PM_L2_ST_HIT ] = { /* 112 */
+	.pme_name = "PM_L2_ST_HIT",
+	.pme_code = 0x000002689E,
+	.pme_short_desc = "All successful store dispatches that were L2Hits",
+	.pme_long_desc = "All successful store dispatches that were L2Hits",
+},
+[ POWER9_PME_PM_DATA_FROM_DMEM ] = { /* 113 */
+	.pme_name = "PM_DATA_FROM_DMEM",
+	.pme_code = 0x000004C04C,
+	.pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a demand load",
+},
+[ POWER9_PME_PM_CMPLU_STALL_DMISS_REMOTE ] = { /* 114 */
+	.pme_name = "PM_CMPLU_STALL_DMISS_REMOTE",
+	.pme_code = 0x000002C01C,
+	.pme_short_desc = "Completion stall by Dcache miss which resolved from remote chip (cache or memory)",
+	.pme_long_desc = "Completion stall by Dcache miss which resolved from remote chip (cache or memory)",
+},
+[ POWER9_PME_PM_LSU2_LDMX_FIN ] = { /* 115 */
+	.pme_name = "PM_LSU2_LDMX_FIN",
+	.pme_code = 0x000000D08C,
+	.pme_short_desc = " New P9 instruction LDMX.",
+	.pme_long_desc = " New P9 instruction LDMX.",
+},
+[ POWER9_PME_PM_L3_LD_MISS ] = { /* 116 */
+	.pme_name = "PM_L3_LD_MISS",
+	.pme_code = 0x00000268A4,
+	.pme_short_desc = "L3 demand LD Miss",
+	.pme_long_desc = "L3 demand LD Miss",
+},
+[ POWER9_PME_PM_DPTEG_FROM_RL4 ] = { /* 117 */
+	.pme_name = "PM_DPTEG_FROM_RL4",
+	.pme_code = 0x000002E04A,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_RADIX_PWC_L3_PDE_FROM_L2 ] = { /* 118 */
+	.pme_name = "PM_RADIX_PWC_L3_PDE_FROM_L2",
+	.pme_code = 0x000002D02A,
+	.pme_short_desc = "A Page Directory Entry was reloaded to a level 3 page walk cache from the core's L2 data cache",
+	.pme_long_desc = "A Page Directory Entry was reloaded to a level 3 page walk cache from the core's L2 data cache",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_RL4_CYC ] = { /* 119 */
+	.pme_name = "PM_MRK_DATA_FROM_RL4_CYC",
+	.pme_code = 0x000004D12A,
+	.pme_short_desc = "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load",
+},
+[ POWER9_PME_PM_TM_SC_CO ] = { /* 120 */
+	.pme_name = "PM_TM_SC_CO",
+	.pme_code = 0x00000160A6,
+	.pme_short_desc = "l3 castout tm Sc line",
+	.pme_long_desc = "l3 castout tm Sc line",
+},
+[ POWER9_PME_PM_L2_SN_SX_I_DONE ] = { /* 121 */
+	.pme_name = "PM_L2_SN_SX_I_DONE",
+	.pme_code = 0x0000036886,
+	.pme_short_desc = "SNP dispatched and went from Sx or Tx to Ix",
+	.pme_long_desc = "SNP dispatched and went from Sx or Tx to Ix",
+},
+[ POWER9_PME_PM_DPTEG_FROM_L3_DISP_CONFLICT ] = { /* 122 */
+	.pme_name = "PM_DPTEG_FROM_L3_DISP_CONFLICT",
+	.pme_code = 0x000003E042,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_ISIDE_L2MEMACC ] = { /* 123 */
+	.pme_name = "PM_ISIDE_L2MEMACC",
+	.pme_code = 0x0000026890,
+	.pme_short_desc = "valid when first beat of data comes in for an i-side fetch where data came from mem(or L4)",
+	.pme_long_desc = "valid when first beat of data comes in for an i-side fetch where data came from mem(or L4)",
+},
+[ POWER9_PME_PM_L3_P0_GRP_PUMP ] = { /* 124 */
+	.pme_name = "PM_L3_P0_GRP_PUMP",
+	.pme_code = 0x00000260B0,
+	.pme_short_desc = "L3 pf sent with grp scope port 0",
+	.pme_long_desc = "L3 pf sent with grp scope port 0",
+},
+[ POWER9_PME_PM_IPTEG_FROM_DL2L3_SHR ] = { /* 125 */
+	.pme_name = "PM_IPTEG_FROM_DL2L3_SHR",
+	.pme_code = 0x0000035048,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request",
+},
+[ POWER9_PME_PM_RADIX_PWC_L3_PDE_FROM_L3 ] = { /* 126 */
+	.pme_name = "PM_RADIX_PWC_L3_PDE_FROM_L3",
+	.pme_code = 0x000001F15C,
+	.pme_short_desc = "A Page Directory Entry was reloaded to a level 3 page walk cache from the core's L3 data cache",
+	.pme_long_desc = "A Page Directory Entry was reloaded to a level 3 page walk cache from the core's L3 data cache",
+},
+[ POWER9_PME_PM_THRESH_MET ] = { /* 127 */
+	.pme_name = "PM_THRESH_MET",
+	.pme_code = 0x00000101EC,
+	.pme_short_desc = "threshold exceeded",
+	.pme_long_desc = "threshold exceeded",
+},
+[ POWER9_PME_PM_DATA_FROM_L2_MEPF ] = { /* 128 */
+	.pme_name = "PM_DATA_FROM_L2_MEPF",
+	.pme_code = 0x000002C040,
+	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load",
+},
+[ POWER9_PME_PM_DISP_STARVED ] = { /* 129 */
+	.pme_name = "PM_DISP_STARVED",
+	.pme_code = 0x0000030008,
+	.pme_short_desc = "Dispatched Starved",
+	.pme_long_desc = "Dispatched Starved",
+},
+[ POWER9_PME_PM_L3_P0_LCO_RTY ] = { /* 130 */
+	.pme_name = "PM_L3_P0_LCO_RTY",
+	.pme_code = 0x00000160B4,
+	.pme_short_desc = "L3 lateral cast out received retry on port 0",
+	.pme_long_desc = "L3 lateral cast out received retry on port 0",
+},
+[ POWER9_PME_PM_NTC_ISSUE_HELD_DARQ_FULL ] = { /* 131 */
+	.pme_name = "PM_NTC_ISSUE_HELD_DARQ_FULL",
+	.pme_code = 0x000001006A,
+	.pme_short_desc = "The NTC instruction is being held at dispatch because there are no slots in the DARQ for it",
+	.pme_long_desc = "The NTC instruction is being held at dispatch because there are no slots in the DARQ for it",
+},
+[ POWER9_PME_PM_L3_RD_USAGE ] = { /* 132 */
+	.pme_name = "PM_L3_RD_USAGE",
+	.pme_code = 0x00000268AC,
+	.pme_short_desc = "rotating sample of 16 RD actives",
+	.pme_long_desc = "rotating sample of 16 RD actives",
+},
+[ POWER9_PME_PM_TLBIE_FIN ] = { /* 133 */
+	.pme_name = "PM_TLBIE_FIN",
+	.pme_code = 0x0000030058,
+	.pme_short_desc = "tlbie finished",
+	.pme_long_desc = "tlbie finished",
+},
+[ POWER9_PME_PM_DPTEG_FROM_LL4 ] = { /* 134 */
+	.pme_name = "PM_DPTEG_FROM_LL4",
+	.pme_code = 0x000001E04C,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_CMPLU_STALL_TLBIE ] = { /* 135 */
+	.pme_name = "PM_CMPLU_STALL_TLBIE",
+	.pme_code = 0x000002E01C,
+	.pme_short_desc = "Finish stall because the NTF instruction was a tlbie waiting for response from L2",
+	.pme_long_desc = "Finish stall because the NTF instruction was a tlbie waiting for response from L2",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L2MISS_CYC ] = { /* 136 */
+	.pme_name = "PM_MRK_DATA_FROM_L2MISS_CYC",
+	.pme_code = 0x0000035152,
+	.pme_short_desc = "Duration in cycles to reload from a localtion other than the local core's L2 due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload from a localtion other than the local core's L2 due to a marked load",
+},
+[ POWER9_PME_PM_LS3_DC_COLLISIONS ] = { /* 137 */
+	.pme_name = "PM_LS3_DC_COLLISIONS",
+	.pme_code = 0x000000D894,
+	.pme_short_desc = "Read-write data cache collisions",
+	.pme_long_desc = "Read-write data cache collisions",
+},
+[ POWER9_PME_PM_L1_ICACHE_MISS ] = { /* 138 */
+	.pme_name = "PM_L1_ICACHE_MISS",
+	.pme_code = 0x00000200FD,
+	.pme_short_desc = "Demand iCache Miss",
+	.pme_long_desc = "Demand iCache Miss",
+},
+[ POWER9_PME_PM_LSU_REJECT_ERAT_MISS ] = { /* 139 */
+	.pme_name = "PM_LSU_REJECT_ERAT_MISS",
+	.pme_code = 0x000002E05C,
+	.pme_short_desc = "LSU Reject due to ERAT (up to 4 per cycles)",
+	.pme_long_desc = "LSU Reject due to ERAT (up to 4 per cycles)",
+},
+[ POWER9_PME_PM_DATA_SYS_PUMP_CPRED ] = { /* 140 */
+	.pme_name = "PM_DATA_SYS_PUMP_CPRED",
+	.pme_code = 0x000003C050,
+	.pme_short_desc = "Initial and Final Pump Scope was system pump (prediction=correct) for a demand load",
+	.pme_long_desc = "Initial and Final Pump Scope was system pump (prediction=correct) for a demand load",
+},
+[ POWER9_PME_PM_MRK_FAB_RSP_RWITM_CYC ] = { /* 141 */
+	.pme_name = "PM_MRK_FAB_RSP_RWITM_CYC",
+	.pme_code = 0x000004F150,
+	.pme_short_desc = "cycles L2 RC took for a rwitm",
+	.pme_long_desc = "cycles L2 RC took for a rwitm",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L3_1_SHR_CYC ] = { /* 142 */
+	.pme_name = "PM_MRK_DATA_FROM_L3_1_SHR_CYC",
+	.pme_code = 0x0000035156,
+	.pme_short_desc = "Duration in cycles to reload with Shared (S) data from another core's L3 on the same chip due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload with Shared (S) data from another core's L3 on the same chip due to a marked load",
+},
+[ POWER9_PME_PM_LSU_FLUSH_UE ] = { /* 143 */
+	.pme_name = "PM_LSU_FLUSH_UE",
+	.pme_code = 0x000000C0B4,
+	.pme_short_desc = "Correctable ECC error on reload data, reported at critical data forward time",
+	.pme_long_desc = "Correctable ECC error on reload data, reported at critical data forward time",
+},
+[ POWER9_PME_PM_BR_PRED_TAKEN_CR ] = { /* 144 */
+	.pme_name = "PM_BR_PRED_TAKEN_CR",
+	.pme_code = 0x00000040B0,
+	.pme_short_desc = "Conditional Branch that had its direction predicted.",
+	.pme_long_desc = "Conditional Branch that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches",
+},
+[ POWER9_PME_PM_INST_FROM_L2_DISP_CONFLICT_OTHER ] = { /* 145 */
+	.pme_name = "PM_INST_FROM_L2_DISP_CONFLICT_OTHER",
+	.pme_code = 0x0000044040,
+	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_DL2L3_SHR ] = { /* 146 */
+	.pme_name = "PM_MRK_DPTEG_FROM_DL2L3_SHR",
+	.pme_code = 0x000003F148,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_DATA_FROM_L2_1_MOD ] = { /* 147 */
+	.pme_name = "PM_DATA_FROM_L2_1_MOD",
+	.pme_code = 0x000004C046,
+	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load",
+},
+[ POWER9_PME_PM_LSU_FLUSH_LHL_SHL ] = { /* 148 */
+	.pme_name = "PM_LSU_FLUSH_LHL_SHL",
+	.pme_code = 0x000000C8B4,
+	.pme_short_desc = "The instruction was flushed because of a sequential load/store consistency.",
+	.pme_long_desc = "The instruction was flushed because of a sequential load/store consistency. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores).",
+},
+[ POWER9_PME_PM_L3_P1_PF_RTY ] = { /* 149 */
+	.pme_name = "PM_L3_P1_PF_RTY",
+	.pme_code = 0x00000268AE,
+	.pme_short_desc = "L3 PF received retry port 3",
+	.pme_long_desc = "L3 PF received retry port 3",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_DL2L3_MOD ] = { /* 150 */
+	.pme_name = "PM_MRK_DPTEG_FROM_DL2L3_MOD",
+	.pme_code = 0x000004F148,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_DFU_BUSY ] = { /* 151 */
+	.pme_name = "PM_DFU_BUSY",
+	.pme_code = 0x000004D04C,
+	.pme_short_desc = "Cycles in which all 4 Decimal Floating Point units are busy.",
+	.pme_long_desc = "Cycles in which all 4 Decimal Floating Point units are busy. The DFU is running at capacity",
+},
+[ POWER9_PME_PM_LSU1_TM_L1_MISS ] = { /* 152 */
+	.pme_name = "PM_LSU1_TM_L1_MISS",
+	.pme_code = 0x000000E89C,
+	.pme_short_desc = "Load tm L1 miss",
+	.pme_long_desc = "Load tm L1 miss",
+},
+[ POWER9_PME_PM_FREQ_UP ] = { /* 153 */
+	.pme_name = "PM_FREQ_UP",
+	.pme_code = 0x000004000C,
+	.pme_short_desc = "Power Management: Above Threshold A",
+	.pme_long_desc = "Power Management: Above Threshold A",
+},
+[ POWER9_PME_PM_DATA_FROM_LMEM ] = { /* 154 */
+	.pme_name = "PM_DATA_FROM_LMEM",
+	.pme_code = 0x000002C048,
+	.pme_short_desc = "The processor's data cache was reloaded from the local chip's Memory due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded from the local chip's Memory due to a demand load",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L2_MEPF ] = { /* 155 */
+	.pme_name = "PM_MRK_DATA_FROM_L2_MEPF",
+	.pme_code = 0x000004C120,
+	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state.",
+	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load",
+},
+[ POWER9_PME_PM_ISIDE_DISP ] = { /* 156 */
+	.pme_name = "PM_ISIDE_DISP",
+	.pme_code = 0x000001688A,
+	.pme_short_desc = "All i-side dispatch attempts",
+	.pme_long_desc = "All i-side dispatch attempts",
+},
+[ POWER9_PME_PM_TM_OUTER_TBEGIN ] = { /* 157 */
+	.pme_name = "PM_TM_OUTER_TBEGIN",
+	.pme_code = 0x0000002094,
+	.pme_short_desc = "Completion time outer tbegin",
+	.pme_long_desc = "Completion time outer tbegin",
+},
+[ POWER9_PME_PM_PMC3_OVERFLOW ] = { /* 158 */
+	.pme_name = "PM_PMC3_OVERFLOW",
+	.pme_code = 0x0000040010,
+	.pme_short_desc = "Overflow from counter 3",
+	.pme_long_desc = "Overflow from counter 3",
+},
+[ POWER9_PME_PM_LSU0_SET_MPRED ] = { /* 159 */
+	.pme_name = "PM_LSU0_SET_MPRED",
+	.pme_code = 0x000000D080,
+	.pme_short_desc = "Set prediction(set-p) miss.",
+	.pme_long_desc = "Set prediction(set-p) miss. The entry was not found in the Set prediction table",
+},
+[ POWER9_PME_PM_INST_FROM_L2_MEPF ] = { /* 160 */
+	.pme_name = "PM_INST_FROM_L2_MEPF",
+	.pme_code = 0x0000024040,
+	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state.",
+	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_L3_P0_NODE_PUMP ] = { /* 161 */
+	.pme_name = "PM_L3_P0_NODE_PUMP",
+	.pme_code = 0x00000160B0,
+	.pme_short_desc = "L3 pf sent with nodal scope port 0",
+	.pme_long_desc = "L3 pf sent with nodal scope port 0",
+},
+[ POWER9_PME_PM_IPTEG_FROM_L3_1_MOD ] = { /* 162 */
+	.pme_name = "PM_IPTEG_FROM_L3_1_MOD",
+	.pme_code = 0x0000025044,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request",
+},
+[ POWER9_PME_PM_L3_PF_USAGE ] = { /* 163 */
+	.pme_name = "PM_L3_PF_USAGE",
+	.pme_code = 0x00000260AC,
+	.pme_short_desc = "rotating sample of 32 PF actives",
+	.pme_long_desc = "rotating sample of 32 PF actives",
+},
+[ POWER9_PME_PM_CMPLU_STALL_BRU ] = { /* 164 */
+	.pme_name = "PM_CMPLU_STALL_BRU",
+	.pme_code = 0x000004D018,
+	.pme_short_desc = "Completion stall due to a Branch Unit",
+	.pme_long_desc = "Completion stall due to a Branch Unit",
+},
+[ POWER9_PME_PM_ISLB_MISS ] = { /* 165 */
+	.pme_name = "PM_ISLB_MISS",
+	.pme_code = 0x000000D8A8,
+	.pme_short_desc = "Instruction SLB Miss - Total of all segment sizes",
+	.pme_long_desc = "Instruction SLB Miss - Total of all segment sizes",
+},
+[ POWER9_PME_PM_CYC ] = { /* 166 */
+	.pme_name = "PM_CYC",
+	.pme_code = 0x000001001E,
+	.pme_short_desc = "Cycles",
+	.pme_long_desc = "Cycles",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L3_1_SHR ] = { /* 167 */
+	.pme_name = "PM_MRK_DATA_FROM_L3_1_SHR",
+	.pme_code = 0x000004D124,
+	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a marked load",
+},
+[ POWER9_PME_PM_IPTEG_FROM_RL2L3_MOD ] = { /* 168 */
+	.pme_name = "PM_IPTEG_FROM_RL2L3_MOD",
+	.pme_code = 0x0000025046,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request",
+},
+[ POWER9_PME_PM_DARQ_10_12_ENTRIES ] = { /* 169 */
+	.pme_name = "PM_DARQ_10_12_ENTRIES",
+	.pme_code = 0x000001D058,
+	.pme_short_desc = "Cycles in which 10 or more DARQ entries (out of 12) are in use",
+	.pme_long_desc = "Cycles in which 10 or more DARQ entries (out of 12) are in use",
+},
+[ POWER9_PME_PM_LSU2_3_LRQF_FULL_CYC ] = { /* 170 */
+	.pme_name = "PM_LSU2_3_LRQF_FULL_CYC",
+	.pme_code = 0x000000D8BC,
+	.pme_short_desc = "Counts the number of cycles the LRQF is full.",
+	.pme_long_desc = "Counts the number of cycles the LRQF is full. LRQF is the queue that holds loads between finish and completion. If it fills up, instructions stay in LRQ until completion, potentially backing up the LRQ",
+},
+[ POWER9_PME_PM_DECODE_FUSION_OP_PRESERV ] = { /* 171 */
+	.pme_name = "PM_DECODE_FUSION_OP_PRESERV",
+	.pme_code = 0x0000005088,
+	.pme_short_desc = "Destructive op operand preservation",
+	.pme_long_desc = "Destructive op operand preservation",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_L2_MEPF ] = { /* 172 */
+	.pme_name = "PM_MRK_DPTEG_FROM_L2_MEPF",
+	.pme_code = 0x000002F140,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_MRK_L1_RELOAD_VALID ] = { /* 173 */
+	.pme_name = "PM_MRK_L1_RELOAD_VALID",
+	.pme_code = 0x00000101EA,
+	.pme_short_desc = "Marked demand reload",
+	.pme_long_desc = "Marked demand reload",
+},
+[ POWER9_PME_PM_LSU2_SET_MPRED ] = { /* 174 */
+	.pme_name = "PM_LSU2_SET_MPRED",
+	.pme_code = 0x000000D084,
+	.pme_short_desc = "Set prediction(set-p) miss.",
+	.pme_long_desc = "Set prediction(set-p) miss. The entry was not found in the Set prediction table",
+},
+[ POWER9_PME_PM_1PLUS_PPC_CMPL ] = { /* 175 */
+	.pme_name = "PM_1PLUS_PPC_CMPL",
+	.pme_code = 0x00000100F2,
+	.pme_short_desc = "1 or more ppc insts finished",
+	.pme_long_desc = "1 or more ppc insts finished",
+},
+[ POWER9_PME_PM_DATA_FROM_LL4 ] = { /* 176 */
+	.pme_name = "PM_DATA_FROM_LL4",
+	.pme_code = 0x000001C04C,
+	.pme_short_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to a demand load",
+},
+[ POWER9_PME_PM_CMPLU_STALL_DMISS_L3MISS ] = { /* 177 */
+	.pme_name = "PM_CMPLU_STALL_DMISS_L3MISS",
+	.pme_code = 0x000004C01A,
+	.pme_short_desc = "Completion stall due to cache miss resolving missed the L3",
+	.pme_long_desc = "Completion stall due to cache miss resolving missed the L3",
+},
+[ POWER9_PME_PM_TM_CAP_OVERFLOW ] = { /* 178 */
+	.pme_name = "PM_TM_CAP_OVERFLOW",
+	.pme_code = 0x000004608C,
+	.pme_short_desc = "TM Footprint Capactiy Overflow",
+	.pme_long_desc = "TM Footprint Capactiy Overflow",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_LMEM ] = { /* 179 */
+	.pme_name = "PM_MRK_DPTEG_FROM_LMEM",
+	.pme_code = 0x000002F148,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_LSU3_FALSE_LHS ] = { /* 180 */
+	.pme_name = "PM_LSU3_FALSE_LHS",
+	.pme_code = 0x000000C8A4,
+	.pme_short_desc = "False LHS match detected",
+	.pme_long_desc = "False LHS match detected",
+},
+[ POWER9_PME_PM_THRESH_EXC_512 ] = { /* 181 */
+	.pme_name = "PM_THRESH_EXC_512",
+	.pme_code = 0x00000201E8,
+	.pme_short_desc = "Threshold counter exceeded a value of 512",
+	.pme_long_desc = "Threshold counter exceeded a value of 512",
+},
+[ POWER9_PME_PM_RADIX_PWC_L1_PDE_FROM_L2 ] = { /* 182 */
+	.pme_name = "PM_RADIX_PWC_L1_PDE_FROM_L2",
+	.pme_code = 0x000002D026,
+	.pme_short_desc = "A Page Directory Entry was reloaded to a level 1 page walk cache from the core's L2 data cache",
+	.pme_long_desc = "A Page Directory Entry was reloaded to a level 1 page walk cache from the core's L2 data cache",
+},
+[ POWER9_PME_PM_HWSYNC ] = { /* 183 */
+	.pme_name = "PM_HWSYNC",
+	.pme_code = 0x00000050A0,
+	.pme_short_desc = "Hwsync instruction decoded and transferred",
+	.pme_long_desc = "Hwsync instruction decoded and transferred",
+},
+[ POWER9_PME_PM_TM_FAIL_FOOTPRINT_OVERFLOW ] = { /* 184 */
+	.pme_name = "PM_TM_FAIL_FOOTPRINT_OVERFLOW",
+	.pme_code = 0x00000020A8,
+	.pme_short_desc = "TM aborted because the tracking limit for transactional storage accesses was exceeded.",
+	.pme_long_desc = "TM aborted because the tracking limit for transactional storage accesses was exceeded.. Asynchronous",
+},
+[ POWER9_PME_PM_INST_SYS_PUMP_MPRED_RTY ] = { /* 185 */
+	.pme_name = "PM_INST_SYS_PUMP_MPRED_RTY",
+	.pme_code = 0x0000044050,
+	.pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch",
+	.pme_long_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch",
+},
+[ POWER9_PME_PM_ICT_NOSLOT_DISP_HELD_HB_FULL ] = { /* 186 */
+	.pme_name = "PM_ICT_NOSLOT_DISP_HELD_HB_FULL",
+	.pme_code = 0x0000030018,
+	.pme_short_desc = "Ict empty for this thread due to dispatch holds because the History Buffer was full.",
+	.pme_long_desc = "Ict empty for this thread due to dispatch holds because the History Buffer was full. Could be GPR/VSR/VMR/FPR/CR/XVF",
+},
+[ POWER9_PME_PM_DC_DEALLOC_NO_CONF ] = { /* 187 */
+	.pme_name = "PM_DC_DEALLOC_NO_CONF",
+	.pme_code = 0x000000F8AC,
+	.pme_short_desc = "A demand load referenced a line in an active fuzzy prefetch stream.",
+	.pme_long_desc = "A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up)",
+},
+[ POWER9_PME_PM_CMPLU_STALL_VFXLONG ] = { /* 188 */
+	.pme_name = "PM_CMPLU_STALL_VFXLONG",
+	.pme_code = 0x000002E018,
+	.pme_short_desc = "Completion stall due to a long latency vector fixed point instruction (division, square root)",
+	.pme_long_desc = "Completion stall due to a long latency vector fixed point instruction (division, square root)",
+},
+[ POWER9_PME_PM_MEM_LOC_THRESH_IFU ] = { /* 189 */
+	.pme_name = "PM_MEM_LOC_THRESH_IFU",
+	.pme_code = 0x0000010058,
+	.pme_short_desc = "Local Memory above threshold for IFU speculation control",
+	.pme_long_desc = "Local Memory above threshold for IFU speculation control",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L3_CYC ] = { /* 190 */
+	.pme_name = "PM_MRK_DATA_FROM_L3_CYC",
+	.pme_code = 0x0000035154,
+	.pme_short_desc = "Duration in cycles to reload from local core's L3 due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload from local core's L3 due to a marked load",
+},
+[ POWER9_PME_PM_PTE_PREFETCH ] = { /* 191 */
+	.pme_name = "PM_PTE_PREFETCH",
+	.pme_code = 0x000000F084,
+	.pme_short_desc = "PTE prefetches",
+	.pme_long_desc = "PTE prefetches",
+},
+[ POWER9_PME_PM_CMPLU_STALL_STORE_PIPE_ARB ] = { /* 192 */
+	.pme_name = "PM_CMPLU_STALL_STORE_PIPE_ARB",
+	.pme_code = 0x000004C010,
+	.pme_short_desc = "Finish stall because the NTF instruction was a store waiting for the next relaunch opportunity after an internal reject.",
+	.pme_long_desc = "Finish stall because the NTF instruction was a store waiting for the next relaunch opportunity after an internal reject. This means the instruction is ready to relaunch and tried once but lost arbitration",
+},
+[ POWER9_PME_PM_CMPLU_STALL_SLB ] = { /* 193 */
+	.pme_name = "PM_CMPLU_STALL_SLB",
+	.pme_code = 0x000001E052,
+	.pme_short_desc = "Finish stall because the NTF instruction was awaiting L2 response for an SLB",
+	.pme_long_desc = "Finish stall because the NTF instruction was awaiting L2 response for an SLB",
+},
+[ POWER9_PME_PM_MRK_DERAT_MISS_4K ] = { /* 194 */
+	.pme_name = "PM_MRK_DERAT_MISS_4K",
+	.pme_code = 0x000002D150,
+	.pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 4K",
+	.pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 4K",
+},
+[ POWER9_PME_PM_CMPLU_STALL_LSU_MFSPR ] = { /* 195 */
+	.pme_name = "PM_CMPLU_STALL_LSU_MFSPR",
+	.pme_code = 0x0000034056,
+	.pme_short_desc = "Finish stall because the NTF instruction was a mfspr instruction targeting an LSU SPR and it was waiting for the register data to be returned",
+	.pme_long_desc = "Finish stall because the NTF instruction was a mfspr instruction targeting an LSU SPR and it was waiting for the register data to be returned",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_L3_1_ECO_SHR ] = { /* 196 */
+	.pme_name = "PM_MRK_DPTEG_FROM_L3_1_ECO_SHR",
+	.pme_code = 0x000003F144,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_VSU_DP_FSQRT_FDIV ] = { /* 197 */
+	.pme_name = "PM_VSU_DP_FSQRT_FDIV",
+	.pme_code = 0x000003D058,
+	.pme_short_desc = "vector versions of fdiv,fsqrt",
+	.pme_long_desc = "vector versions of fdiv,fsqrt",
+},
+[ POWER9_PME_PM_IPTEG_FROM_L3_1_ECO_SHR ] = { /* 198 */
+	.pme_name = "PM_IPTEG_FROM_L3_1_ECO_SHR",
+	.pme_code = 0x0000035044,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request",
+},
+[ POWER9_PME_PM_L3_P0_LCO_DATA ] = { /* 199 */
+	.pme_name = "PM_L3_P0_LCO_DATA",
+	.pme_code = 0x00000260AA,
+	.pme_short_desc = "lco sent with data port 0",
+	.pme_long_desc = "lco sent with data port 0",
+},
+[ POWER9_PME_PM_RUN_INST_CMPL ] = { /* 200 */
+	.pme_name = "PM_RUN_INST_CMPL",
+	.pme_code = 0x00000400FA,
+	.pme_short_desc = "Run_Instructions",
+	.pme_long_desc = "Run_Instructions",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_OFF_CHIP_CACHE ] = { /* 201 */
+	.pme_name = "PM_MRK_DATA_FROM_OFF_CHIP_CACHE",
+	.pme_code = 0x000002D120,
+	.pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load",
+},
+[ POWER9_PME_PM_MRK_TEND_FAIL ] = { /* 202 */
+	.pme_name = "PM_MRK_TEND_FAIL",
+	.pme_code = 0x00000028A4,
+	.pme_short_desc = "Nested or not nested tend failed for a marked tend instruction",
+	.pme_long_desc = "Nested or not nested tend failed for a marked tend instruction",
+},
+[ POWER9_PME_PM_MRK_VSU_FIN ] = { /* 203 */
+	.pme_name = "PM_MRK_VSU_FIN",
+	.pme_code = 0x0000030132,
+	.pme_short_desc = "VSU marked instr finish",
+	.pme_long_desc = "VSU marked instr finish",
+},
+[ POWER9_PME_PM_DATA_FROM_L3_1_ECO_MOD ] = { /* 204 */
+	.pme_name = "PM_DATA_FROM_L3_1_ECO_MOD",
+	.pme_code = 0x000004C044,
+	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a demand load",
+},
+[ POWER9_PME_PM_RUN_SPURR ] = { /* 205 */
+	.pme_name = "PM_RUN_SPURR",
+	.pme_code = 0x0000010008,
+	.pme_short_desc = "Run SPURR",
+	.pme_long_desc = "Run SPURR",
+},
+[ POWER9_PME_PM_ST_CAUSED_FAIL ] = { /* 206 */
+	.pme_name = "PM_ST_CAUSED_FAIL",
+	.pme_code = 0x000001608C,
+	.pme_short_desc = "Non TM St caused any thread to fail",
+	.pme_long_desc = "Non TM St caused any thread to fail",
+},
+[ POWER9_PME_PM_SNOOP_TLBIE ] = { /* 207 */
+	.pme_name = "PM_SNOOP_TLBIE",
+	.pme_code = 0x000000F880,
+	.pme_short_desc = "TLBIE snoop",
+	.pme_long_desc = "TLBIE snoop",
+},
+[ POWER9_PME_PM_PMC1_SAVED ] = { /* 208 */
+	.pme_name = "PM_PMC1_SAVED",
+	.pme_code = 0x000004D010,
+	.pme_short_desc = "PMC1 Rewind Value saved",
+	.pme_long_desc = "PMC1 Rewind Value saved",
+},
+[ POWER9_PME_PM_DATA_FROM_L3MISS ] = { /* 209 */
+	.pme_name = "PM_DATA_FROM_L3MISS",
+	.pme_code = 0x00000300FE,
+	.pme_short_desc = "Demand LD - L3 Miss (not L2 hit and not L3 hit)",
+	.pme_long_desc = "Demand LD - L3 Miss (not L2 hit and not L3 hit)",
+},
+[ POWER9_PME_PM_DATA_FROM_ON_CHIP_CACHE ] = { /* 210 */
+	.pme_name = "PM_DATA_FROM_ON_CHIP_CACHE",
+	.pme_code = 0x000001C048,
+	.pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a demand load",
+},
+[ POWER9_PME_PM_DTLB_MISS_16G ] = { /* 211 */
+	.pme_name = "PM_DTLB_MISS_16G",
+	.pme_code = 0x000001C058,
+	.pme_short_desc = "Data TLB Miss page size 16G",
+	.pme_long_desc = "Data TLB Miss page size 16G",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_DMEM ] = { /* 212 */
+	.pme_name = "PM_MRK_DPTEG_FROM_DMEM",
+	.pme_code = 0x000004F14C,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_ICT_NOSLOT_IC_L3MISS ] = { /* 213 */
+	.pme_name = "PM_ICT_NOSLOT_IC_L3MISS",
+	.pme_code = 0x000004E010,
+	.pme_short_desc = "Ict empty for this thread due to icache misses that were sourced from beyond the local L3.",
+	.pme_long_desc = "Ict empty for this thread due to icache misses that were sourced from beyond the local L3. The source could be local/remote/distant memory or another core's cache",
+},
+[ POWER9_PME_PM_FLUSH ] = { /* 214 */
+	.pme_name = "PM_FLUSH",
+	.pme_code = 0x00000400F8,
+	.pme_short_desc = "Flush (any type)",
+	.pme_long_desc = "Flush (any type)",
+},
+[ POWER9_PME_PM_LSU_FLUSH_OTHER ] = { /* 215 */
+	.pme_name = "PM_LSU_FLUSH_OTHER",
+	.pme_code = 0x000000C0BC,
+	.pme_short_desc = "Other LSU flushes including: Sync (sync ack from L2 caused search of LRQ for oldest snooped load, This will either signal a Precise Flush of the oldest snooped loa or a Flush Next PPC)",
+	.pme_long_desc = "Other LSU flushes including: Sync (sync ack from L2 caused search of LRQ for oldest snooped load, This will either signal a Precise Flush of the oldest snooped loa or a Flush Next PPC)",
+},
+[ POWER9_PME_PM_LS1_LAUNCH_HELD_PREF ] = { /* 216 */
+	.pme_name = "PM_LS1_LAUNCH_HELD_PREF",
+	.pme_code = 0x000000C89C,
+	.pme_short_desc = "Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle",
+	.pme_long_desc = "Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle",
+},
+[ POWER9_PME_PM_L2_LD_HIT ] = { /* 217 */
+	.pme_name = "PM_L2_LD_HIT",
+	.pme_code = 0x000002609E,
+	.pme_short_desc = "All successful load dispatches that were L2 hits",
+	.pme_long_desc = "All successful load dispatches that were L2 hits",
+},
+[ POWER9_PME_PM_LSU2_VECTOR_LD_FIN ] = { /* 218 */
+	.pme_name = "PM_LSU2_VECTOR_LD_FIN",
+	.pme_code = 0x000000C084,
+	.pme_short_desc = "A vector load instruction finished.",
+	.pme_long_desc = "A vector load instruction finished. The ops considered in this category are lxv*, lvx*, lve*, lxsi*zx, lxvwsx, lxsd, lxssp, lxvl, lxvll, lxvb16x, lxvh8x, lxv, lxvx",
+},
+[ POWER9_PME_PM_LSU_FLUSH_EMSH ] = { /* 219 */
+	.pme_name = "PM_LSU_FLUSH_EMSH",
+	.pme_code = 0x000000C0B0,
+	.pme_short_desc = "An ERAT miss was detected after a set-p hit.",
+	.pme_long_desc = "An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due to tlbmiss and the instruction gets flushed because the instruction was working on the wrong address",
+},
+[ POWER9_PME_PM_IC_PREF_REQ ] = { /* 220 */
+	.pme_name = "PM_IC_PREF_REQ",
+	.pme_code = 0x0000004888,
+	.pme_short_desc = "Instruction prefetch requests",
+	.pme_long_desc = "Instruction prefetch requests",
+},
+[ POWER9_PME_PM_DPTEG_FROM_L2_1_SHR ] = { /* 221 */
+	.pme_name = "PM_DPTEG_FROM_L2_1_SHR",
+	.pme_code = 0x000003E046,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_XLATE_RADIX_MODE ] = { /* 222 */
+	.pme_name = "PM_XLATE_RADIX_MODE",
+	.pme_code = 0x000000F898,
+	.pme_short_desc = "LSU reports every cycle the thread is in radix translation mode (as opposed to HPT mode)",
+	.pme_long_desc = "LSU reports every cycle the thread is in radix translation mode (as opposed to HPT mode)",
+},
+[ POWER9_PME_PM_L3_LD_HIT ] = { /* 223 */
+	.pme_name = "PM_L3_LD_HIT",
+	.pme_code = 0x00000260A4,
+	.pme_short_desc = "L3 demand LD Hits",
+	.pme_long_desc = "L3 demand LD Hits",
+},
+[ POWER9_PME_PM_DARQ_7_9_ENTRIES ] = { /* 224 */
+	.pme_name = "PM_DARQ_7_9_ENTRIES",
+	.pme_code = 0x000002E050,
+	.pme_short_desc = "Cycles in which 7,8, or 9 DARQ entries (out of 12) are in use",
+	.pme_long_desc = "Cycles in which 7,8, or 9 DARQ entries (out of 12) are in use",
+},
+[ POWER9_PME_PM_CMPLU_STALL_EXEC_UNIT ] = { /* 225 */
+	.pme_name = "PM_CMPLU_STALL_EXEC_UNIT",
+	.pme_code = 0x000002D018,
+	.pme_short_desc = "Completion stall due to execution units (FXU/VSU/CRU)",
+	.pme_long_desc = "Completion stall due to execution units (FXU/VSU/CRU)",
+},
+[ POWER9_PME_PM_DISP_HELD ] = { /* 226 */
+	.pme_name = "PM_DISP_HELD",
+	.pme_code = 0x0000010006,
+	.pme_short_desc = "Dispatch Held",
+	.pme_long_desc = "Dispatch Held",
+},
+[ POWER9_PME_PM_TM_FAIL_CONF_TM ] = { /* 227 */
+	.pme_name = "PM_TM_FAIL_CONF_TM",
+	.pme_code = 0x00000020AC,
+	.pme_short_desc = "TM aborted because a conflict occurred with another transaction.",
+	.pme_long_desc = "TM aborted because a conflict occurred with another transaction.",
+},
+[ POWER9_PME_PM_LS0_DC_COLLISIONS ] = { /* 228 */
+	.pme_name = "PM_LS0_DC_COLLISIONS",
+	.pme_code = 0x000000D090,
+	.pme_short_desc = "Read-write data cache collisions",
+	.pme_long_desc = "Read-write data cache collisions",
+},
+[ POWER9_PME_PM_L2_LD ] = { /* 229 */
+	.pme_name = "PM_L2_LD",
+	.pme_code = 0x0000016080,
+	.pme_short_desc = "All successful D-side Load dispatches for this thread",
+	.pme_long_desc = "All successful D-side Load dispatches for this thread",
+},
+[ POWER9_PME_PM_BTAC_GOOD_RESULT ] = { /* 230 */
+	.pme_name = "PM_BTAC_GOOD_RESULT",
+	.pme_code = 0x00000058B0,
+	.pme_short_desc = "BTAC predicts a taken branch and the BHT agrees, and the target address is correct",
+	.pme_long_desc = "BTAC predicts a taken branch and the BHT agrees, and the target address is correct",
+},
+[ POWER9_PME_PM_TEND_PEND_CYC ] = { /* 231 */
+	.pme_name = "PM_TEND_PEND_CYC",
+	.pme_code = 0x000000E8B0,
+	.pme_short_desc = "TEND latency per thread",
+	.pme_long_desc = "TEND latency per thread",
+},
+[ POWER9_PME_PM_MRK_DCACHE_RELOAD_INTV ] = { /* 232 */
+	.pme_name = "PM_MRK_DCACHE_RELOAD_INTV",
+	.pme_code = 0x0000040118,
+	.pme_short_desc = "Combined Intervention event",
+	.pme_long_desc = "Combined Intervention event",
+},
+[ POWER9_PME_PM_DISP_HELD_HB_FULL ] = { /* 233 */
+	.pme_name = "PM_DISP_HELD_HB_FULL",
+	.pme_code = 0x000003D05C,
+	.pme_short_desc = "Dispatch held due to History Buffer full.",
+	.pme_long_desc = "Dispatch held due to History Buffer full. Could be GPR/VSR/VMR/FPR/CR/XVF",
+},
+[ POWER9_PME_PM_TM_TRESUME ] = { /* 234 */
+	.pme_name = "PM_TM_TRESUME",
+	.pme_code = 0x00000020A4,
+	.pme_short_desc = "TM resume instruction completed",
+	.pme_long_desc = "TM resume instruction completed",
+},
+[ POWER9_PME_PM_MRK_LSU_FLUSH_SAO ] = { /* 235 */
+	.pme_name = "PM_MRK_LSU_FLUSH_SAO",
+	.pme_code = 0x000000D0A4,
+	.pme_short_desc = "A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush",
+	.pme_long_desc = "A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush",
+},
+[ POWER9_PME_PM_LS0_TM_DISALLOW ] = { /* 236 */
+	.pme_name = "PM_LS0_TM_DISALLOW",
+	.pme_code = 0x000000E0B4,
+	.pme_short_desc = "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it",
+	.pme_long_desc = "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it",
+},
+[ POWER9_PME_PM_DPTEG_FROM_OFF_CHIP_CACHE ] = { /* 237 */
+	.pme_name = "PM_DPTEG_FROM_OFF_CHIP_CACHE",
+	.pme_code = 0x000004E04A,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_RC0_BUSY ] = { /* 238 */
+	.pme_name = "PM_RC0_BUSY",
+	.pme_code = 0x000002608E,
+	.pme_short_desc = "RC mach 0 Busy.",
+	.pme_long_desc = "RC mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)",
+},
+[ POWER9_PME_PM_LSU1_TM_L1_HIT ] = { /* 239 */
+	.pme_name = "PM_LSU1_TM_L1_HIT",
+	.pme_code = 0x000000E894,
+	.pme_short_desc = "Load tm hit in L1",
+	.pme_long_desc = "Load tm hit in L1",
+},
+[ POWER9_PME_PM_TB_BIT_TRANS ] = { /* 240 */
+	.pme_name = "PM_TB_BIT_TRANS",
+	.pme_code = 0x00000300F8,
+	.pme_short_desc = "timebase event",
+	.pme_long_desc = "timebase event",
+},
+[ POWER9_PME_PM_DPTEG_FROM_L2_NO_CONFLICT ] = { /* 241 */
+	.pme_name = "PM_DPTEG_FROM_L2_NO_CONFLICT",
+	.pme_code = 0x000001E040,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_L3_1_MOD ] = { /* 242 */
+	.pme_name = "PM_MRK_DPTEG_FROM_L3_1_MOD",
+	.pme_code = 0x000002F144,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a marked data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT ] = { /* 243 */
+	.pme_name = "PM_MRK_DATA_FROM_L2_NO_CONFLICT",
+	.pme_code = 0x000002C120,
+	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to a marked load",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_LL4_CYC ] = { /* 244 */
+	.pme_name = "PM_MRK_DATA_FROM_LL4_CYC",
+	.pme_code = 0x000002C12E,
+	.pme_short_desc = "Duration in cycles to reload from the local chip's L4 cache due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload from the local chip's L4 cache due to a marked load",
+},
+[ POWER9_PME_PM_INST_FROM_OFF_CHIP_CACHE ] = { /* 245 */
+	.pme_name = "PM_INST_FROM_OFF_CHIP_CACHE",
+	.pme_code = 0x000004404A,
+	.pme_short_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_L3_CO_L31 ] = { /* 246 */
+	.pme_name = "PM_L3_CO_L31",
+	.pme_code = 0x00000268A0,
+	.pme_short_desc = "L3 CO to L3.",
+	.pme_long_desc = "L3 CO to L3.1 OR of port 0 and 1 ( lossy)",
+},
+[ POWER9_PME_PM_CMPLU_STALL_CRYPTO ] = { /* 247 */
+	.pme_name = "PM_CMPLU_STALL_CRYPTO",
+	.pme_code = 0x000004C01E,
+	.pme_short_desc = "Finish stall because the NTF instruction was routed to the crypto execution pipe and was waiting to finish",
+	.pme_long_desc = "Finish stall because the NTF instruction was routed to the crypto execution pipe and was waiting to finish",
+},
+[ POWER9_PME_PM_RADIX_PWC_L1_PDE_FROM_L3 ] = { /* 248 */
+	.pme_name = "PM_RADIX_PWC_L1_PDE_FROM_L3",
+	.pme_code = 0x000003F058,
+	.pme_short_desc = "A Page Directory Entry was reloaded to a level 1 page walk cache from the core's L3 data cache",
+	.pme_long_desc = "A Page Directory Entry was reloaded to a level 1 page walk cache from the core's L3 data cache",
+},
+[ POWER9_PME_PM_ICT_EMPTY_CYC ] = { /* 249 */
+	.pme_name = "PM_ICT_EMPTY_CYC",
+	.pme_code = 0x0000020004,
+	.pme_short_desc = "Cycles in which the ICT is completely empty.",
+	.pme_long_desc = "Cycles in which the ICT is completely empty. No itags are assigned to any thread",
+},
+[ POWER9_PME_PM_BR_UNCOND ] = { /* 250 */
+	.pme_name = "PM_BR_UNCOND",
+	.pme_code = 0x00000040A0,
+	.pme_short_desc = "Unconditional Branch Completed.",
+	.pme_long_desc = "Unconditional Branch Completed. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve.",
+},
+[ POWER9_PME_PM_DERAT_MISS_2M ] = { /* 251 */
+	.pme_name = "PM_DERAT_MISS_2M",
+	.pme_code = 0x000001C05A,
+	.pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 2M.",
+	.pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 2M. Implies radix translation",
+},
+[ POWER9_PME_PM_PMC4_REWIND ] = { /* 252 */
+	.pme_name = "PM_PMC4_REWIND",
+	.pme_code = 0x0000010020,
+	.pme_short_desc = "PMC4 Rewind Event",
+	.pme_long_desc = "PMC4 Rewind Event",
+},
+[ POWER9_PME_PM_L2_RCLD_DISP ] = { /* 253 */
+	.pme_name = "PM_L2_RCLD_DISP",
+	.pme_code = 0x0000016084,
+	.pme_short_desc = "L2 RC load dispatch attempt",
+	.pme_long_desc = "L2 RC load dispatch attempt",
+},
+[ POWER9_PME_PM_CMPLU_STALL_DMISS_L2L3_CONFLICT ] = { /* 254 */
+	.pme_name = "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT",
+	.pme_code = 0x000004C016,
+	.pme_short_desc = "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict",
+	.pme_long_desc = "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict",
+},
+[ POWER9_PME_PM_TAKEN_BR_MPRED_CMPL ] = { /* 255 */
+	.pme_name = "PM_TAKEN_BR_MPRED_CMPL",
+	.pme_code = 0x0000020056,
+	.pme_short_desc = "Total number of taken branches that were incorrectly predicted as not-taken.",
+	.pme_long_desc = "Total number of taken branches that were incorrectly predicted as not-taken. This event counts branches completed and does not include speculative instructions",
+},
+[ POWER9_PME_PM_THRD_PRIO_2_3_CYC ] = { /* 256 */
+	.pme_name = "PM_THRD_PRIO_2_3_CYC",
+	.pme_code = 0x00000048BC,
+	.pme_short_desc = "Cycles thread running at priority level 2 or 3",
+	.pme_long_desc = "Cycles thread running at priority level 2 or 3",
+},
+[ POWER9_PME_PM_DATA_FROM_DL4 ] = { /* 257 */
+	.pme_name = "PM_DATA_FROM_DL4",
+	.pme_code = 0x000003C04C,
+	.pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load",
+},
+[ POWER9_PME_PM_CMPLU_STALL_DPLONG ] = { /* 258 */
+	.pme_name = "PM_CMPLU_STALL_DPLONG",
+	.pme_code = 0x000003405C,
+	.pme_short_desc = "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish.",
+	.pme_long_desc = "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Qualified by NOT vector AND multicycle",
+},
+[ POWER9_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = { /* 259 */
+	.pme_name = "PM_IC_DEMAND_L2_BHT_REDIRECT",
+	.pme_code = 0x0000004098,
+	.pme_short_desc = "L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles)",
+	.pme_long_desc = "L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles)",
+},
+[ POWER9_PME_PM_MRK_FAB_RSP_BKILL ] = { /* 260 */
+	.pme_name = "PM_MRK_FAB_RSP_BKILL",
+	.pme_code = 0x0000040154,
+	.pme_short_desc = "Marked store had to do a bkill",
+	.pme_long_desc = "Marked store had to do a bkill",
+},
+[ POWER9_PME_PM_LSU_DERAT_MISS ] = { /* 261 */
+	.pme_name = "PM_LSU_DERAT_MISS",
+	.pme_code = 0x00000200F6,
+	.pme_short_desc = "DERAT Reloaded due to a DERAT miss",
+	.pme_long_desc = "DERAT Reloaded due to a DERAT miss",
+},
+[ POWER9_PME_PM_IC_PREF_CANCEL_L2 ] = { /* 262 */
+	.pme_name = "PM_IC_PREF_CANCEL_L2",
+	.pme_code = 0x0000004094,
+	.pme_short_desc = "L2 Squashed a demand or prefetch request",
+	.pme_long_desc = "L2 Squashed a demand or prefetch request",
+},
+[ POWER9_PME_PM_MRK_NTC_CYC ] = { /* 263 */
+	.pme_name = "PM_MRK_NTC_CYC",
+	.pme_code = 0x000002011C,
+	.pme_short_desc = "Cycles during which the marked instruction is next to complete (completion is held up because the marked instruction hasn't completed yet)",
+	.pme_long_desc = "Cycles during which the marked instruction is next to complete (completion is held up because the marked instruction hasn't completed yet)",
+},
+[ POWER9_PME_PM_STCX_FIN ] = { /* 264 */
+	.pme_name = "PM_STCX_FIN",
+	.pme_code = 0x000002E014,
+	.pme_short_desc = "Number of stcx instructions finished.",
+	.pme_long_desc = "Number of stcx instructions finished. This includes instructions in the speculative path of a branch that may be flushed",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L3_MEPF ] = { /* 265 */
+	.pme_name = "PM_MRK_DATA_FROM_L3_MEPF",
+	.pme_code = 0x000002D142,
+	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state.",
+	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load",
+},
+[ POWER9_PME_PM_DC_PREF_FUZZY_CONF ] = { /* 266 */
+	.pme_name = "PM_DC_PREF_FUZZY_CONF",
+	.pme_code = 0x000000F8A8,
+	.pme_short_desc = "A demand load referenced a line in an active fuzzy prefetch stream.",
+	.pme_long_desc = "A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up)",
+},
+[ POWER9_PME_PM_MULT_MRK ] = { /* 267 */
+	.pme_name = "PM_MULT_MRK",
+	.pme_code = 0x000003D15E,
+	.pme_short_desc = "mult marked instr",
+	.pme_long_desc = "mult marked instr",
+},
+[ POWER9_PME_PM_LSU_FLUSH_LARX_STCX ] = { /* 268 */
+	.pme_name = "PM_LSU_FLUSH_LARX_STCX",
+	.pme_code = 0x000000C8B8,
+	.pme_short_desc = "A larx is flushed because an older larx has an LMQ reservation for the same thread.",
+	.pme_long_desc = "A larx is flushed because an older larx has an LMQ reservation for the same thread. A stcx is flushed because an older stcx is in the LMQ. The flush happens when the older larx/stcx relaunches",
+},
+[ POWER9_PME_PM_L3_P1_LCO_NO_DATA ] = { /* 269 */
+	.pme_name = "PM_L3_P1_LCO_NO_DATA",
+	.pme_code = 0x00000168AA,
+	.pme_short_desc = "dataless l3 lco sent port 1",
+	.pme_long_desc = "dataless l3 lco sent port 1",
+},
+[ POWER9_PME_PM_TM_TABORT_TRECLAIM ] = { /* 270 */
+	.pme_name = "PM_TM_TABORT_TRECLAIM",
+	.pme_code = 0x0000002898,
+	.pme_short_desc = "Completion time tabortnoncd, tabortcd, treclaim",
+	.pme_long_desc = "Completion time tabortnoncd, tabortcd, treclaim",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L2_MEPF_CYC ] = { /* 271 */
+	.pme_name = "PM_MRK_DATA_FROM_L2_MEPF_CYC",
+	.pme_code = 0x000003D144,
+	.pme_short_desc = "Duration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf state.",
+	.pme_long_desc = "Duration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load",
+},
+[ POWER9_PME_PM_BR_PRED_CCACHE ] = { /* 272 */
+	.pme_name = "PM_BR_PRED_CCACHE",
+	.pme_code = 0x00000040A4,
+	.pme_short_desc = "Conditional Branch Completed that used the Count Cache for Target Prediction",
+	.pme_long_desc = "Conditional Branch Completed that used the Count Cache for Target Prediction",
+},
+[ POWER9_PME_PM_L3_P1_LCO_DATA ] = { /* 273 */
+	.pme_name = "PM_L3_P1_LCO_DATA",
+	.pme_code = 0x00000268AA,
+	.pme_short_desc = "lco sent with data port 1",
+	.pme_long_desc = "lco sent with data port 1",
+},
+[ POWER9_PME_PM_LINK_STACK_WRONG_ADD_PRED ] = { /* 274 */
+	.pme_name = "PM_LINK_STACK_WRONG_ADD_PRED",
+	.pme_code = 0x0000005098,
+	.pme_short_desc = "Link stack predicts wrong address, because of link stack design limitation or software violating the coding conventions",
+	.pme_long_desc = "Link stack predicts wrong address, because of link stack design limitation or software violating the coding conventions",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_L3 ] = { /* 275 */
+	.pme_name = "PM_MRK_DPTEG_FROM_L3",
+	.pme_code = 0x000004F142,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_MRK_ST_CMPL_INT ] = { /* 276 */
+	.pme_name = "PM_MRK_ST_CMPL_INT",
+	.pme_code = 0x0000030134,
+	.pme_short_desc = "marked store finished with intervention",
+	.pme_long_desc = "marked store finished with intervention",
+},
+[ POWER9_PME_PM_FLUSH_HB_RESTORE_CYC ] = { /* 277 */
+	.pme_name = "PM_FLUSH_HB_RESTORE_CYC",
+	.pme_code = 0x0000002084,
+	.pme_short_desc = "Cycles in which no new instructions can be dispatched to the ICT after a flush.",
+	.pme_long_desc = "Cycles in which no new instructions can be dispatched to the ICT after a flush. History buffer recovery",
+},
+[ POWER9_PME_PM_LS1_PTE_TABLEWALK_CYC ] = { /* 278 */
+	.pme_name = "PM_LS1_PTE_TABLEWALK_CYC",
+	.pme_code = 0x000000E8BC,
+	.pme_short_desc = "Cycles when a tablewalk is pending on this thread on table 1",
+	.pme_long_desc = "Cycles when a tablewalk is pending on this thread on table 1",
+},
+[ POWER9_PME_PM_L3_CI_USAGE ] = { /* 279 */
+	.pme_name = "PM_L3_CI_USAGE",
+	.pme_code = 0x00000168AC,
+	.pme_short_desc = "rotating sample of 16 CI or CO actives",
+	.pme_long_desc = "rotating sample of 16 CI or CO actives",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L3MISS ] = { /* 280 */
+	.pme_name = "PM_MRK_DATA_FROM_L3MISS",
+	.pme_code = 0x00000201E4,
+	.pme_short_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a marked load",
+},
+[ POWER9_PME_PM_DPTEG_FROM_DL4 ] = { /* 281 */
+	.pme_name = "PM_DPTEG_FROM_DL4",
+	.pme_code = 0x000003E04C,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_MRK_STCX_FIN ] = { /* 282 */
+	.pme_name = "PM_MRK_STCX_FIN",
+	.pme_code = 0x0000024056,
+	.pme_short_desc = "Number of marked stcx instructions finished.",
+	.pme_long_desc = "Number of marked stcx instructions finished. This includes instructions in the speculative path of a branch that may be flushed",
+},
+[ POWER9_PME_PM_MRK_LSU_FLUSH_UE ] = { /* 283 */
+	.pme_name = "PM_MRK_LSU_FLUSH_UE",
+	.pme_code = 0x000000D89C,
+	.pme_short_desc = "Correctable ECC error on reload data, reported at critical data forward time",
+	.pme_long_desc = "Correctable ECC error on reload data, reported at critical data forward time",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_MEMORY ] = { /* 284 */
+	.pme_name = "PM_MRK_DATA_FROM_MEMORY",
+	.pme_code = 0x00000201E0,
+	.pme_short_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load",
+},
+[ POWER9_PME_PM_GRP_PUMP_MPRED_RTY ] = { /* 285 */
+	.pme_name = "PM_GRP_PUMP_MPRED_RTY",
+	.pme_code = 0x0000010052,
+	.pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
+	.pme_long_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
+},
+[ POWER9_PME_PM_DPTEG_FROM_L3_1_ECO_SHR ] = { /* 286 */
+	.pme_name = "PM_DPTEG_FROM_L3_1_ECO_SHR",
+	.pme_code = 0x000003E044,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_FLUSH_DISP_TLBIE ] = { /* 287 */
+	.pme_name = "PM_FLUSH_DISP_TLBIE",
+	.pme_code = 0x0000002888,
+	.pme_short_desc = "Dispatch Flush: TLBIE",
+	.pme_long_desc = "Dispatch Flush: TLBIE",
+},
+[ POWER9_PME_PM_DPTEG_FROM_L3MISS ] = { /* 288 */
+	.pme_name = "PM_DPTEG_FROM_L3MISS",
+	.pme_code = 0x000004E04E,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_L3_GRP_GUESS_CORRECT ] = { /* 289 */
+	.pme_name = "PM_L3_GRP_GUESS_CORRECT",
+	.pme_code = 0x00000168B2,
+	.pme_short_desc = "Initial scope=group and data from same group (near) (pred successful)",
+	.pme_long_desc = "Initial scope=group and data from same group (near) (pred successful)",
+},
+[ POWER9_PME_PM_IC_INVALIDATE ] = { /* 290 */
+	.pme_name = "PM_IC_INVALIDATE",
+	.pme_code = 0x0000005888,
+	.pme_short_desc = "Ic line invalidated",
+	.pme_long_desc = "Ic line invalidated",
+},
+[ POWER9_PME_PM_DERAT_MISS_16G ] = { /* 291 */
+	.pme_name = "PM_DERAT_MISS_16G",
+	.pme_code = 0x000004C054,
+	.pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 16G",
+	.pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 16G",
+},
+[ POWER9_PME_PM_SYS_PUMP_MPRED_RTY ] = { /* 292 */
+	.pme_name = "PM_SYS_PUMP_MPRED_RTY",
+	.pme_code = 0x0000040050,
+	.pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
+	.pme_long_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
+},
+[ POWER9_PME_PM_LMQ_MERGE ] = { /* 293 */
+	.pme_name = "PM_LMQ_MERGE",
+	.pme_code = 0x000001002E,
+	.pme_short_desc = "A demand miss collides with a prefetch for the same line",
+	.pme_long_desc = "A demand miss collides with a prefetch for the same line",
+},
+[ POWER9_PME_PM_IPTEG_FROM_LMEM ] = { /* 294 */
+	.pme_name = "PM_IPTEG_FROM_LMEM",
+	.pme_code = 0x0000025048,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction side request",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction side request",
+},
+[ POWER9_PME_PM_L3_LAT_CI_HIT ] = { /* 295 */
+	.pme_name = "PM_L3_LAT_CI_HIT",
+	.pme_code = 0x00000460A2,
+	.pme_short_desc = "L3 Lateral Castins Hit",
+	.pme_long_desc = "L3 Lateral Castins Hit",
+},
+[ POWER9_PME_PM_LSU1_VECTOR_ST_FIN ] = { /* 296 */
+	.pme_name = "PM_LSU1_VECTOR_ST_FIN",
+	.pme_code = 0x000000C888,
+	.pme_short_desc = "A vector store instruction finished.",
+	.pme_long_desc = "A vector store instruction finished. The ops considered in this category are stv*, stxv*, stxsi*x, stxsd, and stxssp",
+},
+[ POWER9_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = { /* 297 */
+	.pme_name = "PM_IC_DEMAND_L2_BR_REDIRECT",
+	.pme_code = 0x0000004898,
+	.pme_short_desc = "L2 I cache demand request due to branch Mispredict ( 15 cycle path)",
+	.pme_long_desc = "L2 I cache demand request due to branch Mispredict ( 15 cycle path)",
+},
+[ POWER9_PME_PM_INST_FROM_LMEM ] = { /* 298 */
+	.pme_name = "PM_INST_FROM_LMEM",
+	.pme_code = 0x0000024048,
+	.pme_short_desc = "The processor's Instruction cache was reloaded from the local chip's Memory due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded from the local chip's Memory due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_RL4 ] = { /* 299 */
+	.pme_name = "PM_MRK_DATA_FROM_RL4",
+	.pme_code = 0x000003515C,
+	.pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load",
+},
+[ POWER9_PME_PM_MRK_DTLB_MISS_4K ] = { /* 300 */
+	.pme_name = "PM_MRK_DTLB_MISS_4K",
+	.pme_code = 0x000002D156,
+	.pme_short_desc = "Marked Data TLB Miss page size 4k",
+	.pme_long_desc = "Marked Data TLB Miss page size 4k",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT ] = { /* 301 */
+	.pme_name = "PM_MRK_DATA_FROM_L3_NO_CONFLICT",
+	.pme_code = 0x000003D146,
+	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to a marked load",
+},
+[ POWER9_PME_PM_CMPLU_STALL_NTC_FLUSH ] = { /* 302 */
+	.pme_name = "PM_CMPLU_STALL_NTC_FLUSH",
+	.pme_code = 0x000002E01E,
+	.pme_short_desc = "Completion stall due to ntc flush",
+	.pme_long_desc = "Completion stall due to ntc flush",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC ] = { /* 303 */
+	.pme_name = "PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC",
+	.pme_code = 0x000004C124,
+	.pme_short_desc = "Duration in cycles to reload from local core's L3 without conflict due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload from local core's L3 without conflict due to a marked load",
+},
+[ POWER9_PME_PM_DARQ_0_3_ENTRIES ] = { /* 304 */
+	.pme_name = "PM_DARQ_0_3_ENTRIES",
+	.pme_code = 0x000004D04A,
+	.pme_short_desc = "Cycles in which 3 or less DARQ entries (out of 12) are in use",
+	.pme_long_desc = "Cycles in which 3 or less DARQ entries (out of 12) are in use",
+},
+[ POWER9_PME_PM_DATA_FROM_L3MISS_MOD ] = { /* 305 */
+	.pme_name = "PM_DATA_FROM_L3MISS_MOD",
+	.pme_code = 0x000004C04E,
+	.pme_short_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a demand load",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L2_1_SHR_CYC ] = { /* 306 */
+	.pme_name = "PM_MRK_DATA_FROM_L2_1_SHR_CYC",
+	.pme_code = 0x000001D154,
+	.pme_short_desc = "Duration in cycles to reload with Shared (S) data from another core's L2 on the same chip due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload with Shared (S) data from another core's L2 on the same chip due to a marked load",
+},
+[ POWER9_PME_PM_TAGE_OVERRIDE_WRONG ] = { /* 307 */
+	.pme_name = "PM_TAGE_OVERRIDE_WRONG",
+	.pme_code = 0x00000050B8,
+	.pme_short_desc = "The TAGE overrode BHT direction prediction but it was incorrect.",
+	.pme_long_desc = "The TAGE overrode BHT direction prediction but it was incorrect. Counted at completion for taken branches only",
+},
+[ POWER9_PME_PM_L2_LD_MISS ] = { /* 308 */
+	.pme_name = "PM_L2_LD_MISS",
+	.pme_code = 0x0000026080,
+	.pme_short_desc = "All successful D-Side Load dispatches that were an L2miss for this thread",
+	.pme_long_desc = "All successful D-Side Load dispatches that were an L2miss for this thread",
+},
+[ POWER9_PME_PM_EAT_FULL_CYC ] = { /* 309 */
+	.pme_name = "PM_EAT_FULL_CYC",
+	.pme_code = 0x0000004084,
+	.pme_short_desc = "Cycles No room in EAT",
+	.pme_long_desc = "Cycles No room in EAT",
+},
+[ POWER9_PME_PM_CMPLU_STALL_SPEC_FINISH ] = { /* 310 */
+	.pme_name = "PM_CMPLU_STALL_SPEC_FINISH",
+	.pme_code = 0x0000030028,
+	.pme_short_desc = "Finish stall while waiting for the non-speculative finish of either a stcx waiting for its result or a load waiting for non-critical sectors of data and ECC",
+	.pme_long_desc = "Finish stall while waiting for the non-speculative finish of either a stcx waiting for its result or a load waiting for non-critical sectors of data and ECC",
+},
+[ POWER9_PME_PM_MRK_LSU_FLUSH_LARX_STCX ] = { /* 311 */
+	.pme_name = "PM_MRK_LSU_FLUSH_LARX_STCX",
+	.pme_code = 0x000000D8A4,
+	.pme_short_desc = "A larx is flushed because an older larx has an LMQ reservation for the same thread.",
+	.pme_long_desc = "A larx is flushed because an older larx has an LMQ reservation for the same thread. A stcx is flushed because an older stcx is in the LMQ. The flush happens when the older larx/stcx relaunches",
+},
+[ POWER9_PME_PM_THRESH_EXC_128 ] = { /* 312 */
+	.pme_name = "PM_THRESH_EXC_128",
+	.pme_code = 0x00000401EA,
+	.pme_short_desc = "Threshold counter exceeded a value of 128",
+	.pme_long_desc = "Threshold counter exceeded a value of 128",
+},
+[ POWER9_PME_PM_LMQ_EMPTY_CYC ] = { /* 313 */
+	.pme_name = "PM_LMQ_EMPTY_CYC",
+	.pme_code = 0x000002E05E,
+	.pme_short_desc = "Cycles in which the LMQ has no pending load misses for this thread",
+	.pme_long_desc = "Cycles in which the LMQ has no pending load misses for this thread",
+},
+[ POWER9_PME_PM_RADIX_PWC_L2_PDE_FROM_L3 ] = { /* 314 */
+	.pme_name = "PM_RADIX_PWC_L2_PDE_FROM_L3",
+	.pme_code = 0x000003F05A,
+	.pme_short_desc = "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L3 data cache",
+	.pme_long_desc = "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L3 data cache",
+},
+[ POWER9_PME_PM_MRK_IC_MISS ] = { /* 315 */
+	.pme_name = "PM_MRK_IC_MISS",
+	.pme_code = 0x000004013A,
+	.pme_short_desc = "Marked instruction experienced I cache miss",
+	.pme_long_desc = "Marked instruction experienced I cache miss",
+},
+[ POWER9_PME_PM_L3_P1_GRP_PUMP ] = { /* 316 */
+	.pme_name = "PM_L3_P1_GRP_PUMP",
+	.pme_code = 0x00000268B0,
+	.pme_short_desc = "L3 pf sent with grp scope port 1",
+	.pme_long_desc = "L3 pf sent with grp scope port 1",
+},
+[ POWER9_PME_PM_CMPLU_STALL_TEND ] = { /* 317 */
+	.pme_name = "PM_CMPLU_STALL_TEND",
+	.pme_code = 0x000001E050,
+	.pme_short_desc = "Finish stall because the NTF instruction was a tend instruction awaiting response from L2",
+	.pme_long_desc = "Finish stall because the NTF instruction was a tend instruction awaiting response from L2",
+},
+[ POWER9_PME_PM_PUMP_MPRED ] = { /* 318 */
+	.pme_name = "PM_PUMP_MPRED",
+	.pme_code = 0x0000040052,
+	.pme_short_desc = "Pump misprediction.",
+	.pme_long_desc = "Pump misprediction. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
+},
+[ POWER9_PME_PM_INST_GRP_PUMP_MPRED ] = { /* 319 */
+	.pme_name = "PM_INST_GRP_PUMP_MPRED",
+	.pme_code = 0x000002C05E,
+	.pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for an instruction fetch (demand only)",
+	.pme_long_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for an instruction fetch (demand only)",
+},
+[ POWER9_PME_PM_L1_PREF ] = { /* 320 */
+	.pme_name = "PM_L1_PREF",
+	.pme_code = 0x0000020054,
+	.pme_short_desc = "A data line was written to the L1 due to a hardware or software prefetch",
+	.pme_long_desc = "A data line was written to the L1 due to a hardware or software prefetch",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_LMEM_CYC ] = { /* 321 */
+	.pme_name = "PM_MRK_DATA_FROM_LMEM_CYC",
+	.pme_code = 0x000004D128,
+	.pme_short_desc = "Duration in cycles to reload from the local chip's Memory due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload from the local chip's Memory due to a marked load",
+},
+[ POWER9_PME_PM_LSU_FLUSH_ATOMIC ] = { /* 322 */
+	.pme_name = "PM_LSU_FLUSH_ATOMIC",
+	.pme_code = 0x000000C8A8,
+	.pme_short_desc = "Quad-word loads (lq) are considered atomic because they always span at least 2 slices.",
+	.pme_long_desc = "Quad-word loads (lq) are considered atomic because they always span at least 2 slices. If a snoop or store from another thread changes the data the load is accessing between the 2 or 3 pieces of the lq instruction, the lq will be flushed",
+},
+[ POWER9_PME_PM_L2_DISP_ALL_L2MISS ] = { /* 323 */
+	.pme_name = "PM_L2_DISP_ALL_L2MISS",
+	.pme_code = 0x0000046080,
+	.pme_short_desc = "All successful Ld/St dispatches for this thread that were an L2miss.",
+	.pme_long_desc = "All successful Ld/St dispatches for this thread that were an L2miss.",
+},
+[ POWER9_PME_PM_DATA_FROM_MEMORY ] = { /* 324 */
+	.pme_name = "PM_DATA_FROM_MEMORY",
+	.pme_code = 0x00000400FE,
+	.pme_short_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load",
+},
+[ POWER9_PME_PM_IPTEG_FROM_L3_1_ECO_MOD ] = { /* 325 */
+	.pme_name = "PM_IPTEG_FROM_L3_1_ECO_MOD",
+	.pme_code = 0x0000045044,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request",
+},
+[ POWER9_PME_PM_ISIDE_DISP_FAIL_ADDR ] = { /* 326 */
+	.pme_name = "PM_ISIDE_DISP_FAIL_ADDR",
+	.pme_code = 0x000002608A,
+	.pme_short_desc = "All i-side dispatch attempts that failed due to a addr collision with another machine",
+	.pme_long_desc = "All i-side dispatch attempts that failed due to a addr collision with another machine",
+},
+[ POWER9_PME_PM_CMPLU_STALL_HWSYNC ] = { /* 327 */
+	.pme_name = "PM_CMPLU_STALL_HWSYNC",
+	.pme_code = 0x0000030036,
+	.pme_short_desc = "completion stall due to hwsync",
+	.pme_long_desc = "completion stall due to hwsync",
+},
+[ POWER9_PME_PM_DATA_FROM_L3 ] = { /* 328 */
+	.pme_name = "PM_DATA_FROM_L3",
+	.pme_code = 0x000004C042,
+	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 due to a demand load",
+},
+[ POWER9_PME_PM_PMC2_OVERFLOW ] = { /* 329 */
+	.pme_name = "PM_PMC2_OVERFLOW",
+	.pme_code = 0x0000030010,
+	.pme_short_desc = "Overflow from counter 2",
+	.pme_long_desc = "Overflow from counter 2",
+},
+[ POWER9_PME_PM_LSU0_SRQ_S0_VALID_CYC ] = { /* 330 */
+	.pme_name = "PM_LSU0_SRQ_S0_VALID_CYC",
+	.pme_code = 0x000000D0B4,
+	.pme_short_desc = "Slot 0 of SRQ valid",
+	.pme_long_desc = "Slot 0 of SRQ valid",
+},
+[ POWER9_PME_PM_DPTEG_FROM_LMEM ] = { /* 331 */
+	.pme_name = "PM_DPTEG_FROM_LMEM",
+	.pme_code = 0x000002E048,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_IPTEG_FROM_ON_CHIP_CACHE ] = { /* 332 */
+	.pme_name = "PM_IPTEG_FROM_ON_CHIP_CACHE",
+	.pme_code = 0x0000015048,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request",
+},
+[ POWER9_PME_PM_LSU1_SET_MPRED ] = { /* 333 */
+	.pme_name = "PM_LSU1_SET_MPRED",
+	.pme_code = 0x000000D880,
+	.pme_short_desc = "Set prediction(set-p) miss.",
+	.pme_long_desc = "Set prediction(set-p) miss. The entry was not found in the Set prediction table",
+},
+[ POWER9_PME_PM_DATA_FROM_L3_1_ECO_SHR ] = { /* 334 */
+	.pme_name = "PM_DATA_FROM_L3_1_ECO_SHR",
+	.pme_code = 0x000003C044,
+	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a demand load",
+},
+[ POWER9_PME_PM_INST_FROM_MEMORY ] = { /* 335 */
+	.pme_name = "PM_INST_FROM_MEMORY",
+	.pme_code = 0x000002404C,
+	.pme_short_desc = "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_L3_P1_LCO_RTY ] = { /* 336 */
+	.pme_name = "PM_L3_P1_LCO_RTY",
+	.pme_code = 0x00000168B4,
+	.pme_short_desc = "L3 lateral cast out received retry on port 1",
+	.pme_long_desc = "L3 lateral cast out received retry on port 1",
+},
+[ POWER9_PME_PM_DATA_FROM_L2_1_SHR ] = { /* 337 */
+	.pme_name = "PM_DATA_FROM_L2_1_SHR",
+	.pme_code = 0x000003C046,
+	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load",
+},
+[ POWER9_PME_PM_FLUSH_LSU ] = { /* 338 */
+	.pme_name = "PM_FLUSH_LSU",
+	.pme_code = 0x00000058A4,
+	.pme_short_desc = "LSU flushes.",
+	.pme_long_desc = "LSU flushes. Includes all lsu flushes",
+},
+[ POWER9_PME_PM_CMPLU_STALL_FXLONG ] = { /* 339 */
+	.pme_name = "PM_CMPLU_STALL_FXLONG",
+	.pme_code = 0x000004D016,
+	.pme_short_desc = "Completion stall due to a long latency scalar fixed point instruction (division, square root)",
+	.pme_long_desc = "Completion stall due to a long latency scalar fixed point instruction (division, square root)",
+},
+[ POWER9_PME_PM_CMPLU_STALL_DMISS_LMEM ] = { /* 340 */
+	.pme_name = "PM_CMPLU_STALL_DMISS_LMEM",
+	.pme_code = 0x0000030038,
+	.pme_short_desc = "Completion stall due to cache miss that resolves in local memory",
+	.pme_long_desc = "Completion stall due to cache miss that resolves in local memory",
+},
+[ POWER9_PME_PM_SNP_TM_HIT_M ] = { /* 341 */
+	.pme_name = "PM_SNP_TM_HIT_M",
+	.pme_code = 0x00000360A6,
+	.pme_short_desc = "snp tm st hit m mu",
+	.pme_long_desc = "snp tm st hit m mu",
+},
+[ POWER9_PME_PM_INST_GRP_PUMP_MPRED_RTY ] = { /* 342 */
+	.pme_name = "PM_INST_GRP_PUMP_MPRED_RTY",
+	.pme_code = 0x0000014052,
+	.pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for an instruction fetch",
+	.pme_long_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for an instruction fetch",
+},
+[ POWER9_PME_PM_L2_INST_MISS ] = { /* 343 */
+	.pme_name = "PM_L2_INST_MISS",
+	.pme_code = 0x000004609E,
+	.pme_short_desc = "All successful i-side dispatches that were an L2miss for this thread (excludes i_l2mru_tch reqs)",
+	.pme_long_desc = "All successful i-side dispatches that were an L2miss for this thread (excludes i_l2mru_tch reqs)",
+},
+[ POWER9_PME_PM_CMPLU_STALL_ERAT_MISS ] = { /* 344 */
+	.pme_name = "PM_CMPLU_STALL_ERAT_MISS",
+	.pme_code = 0x000004C012,
+	.pme_short_desc = "Finish stall because the NTF instruction was a load or store that suffered a translation miss",
+	.pme_long_desc = "Finish stall because the NTF instruction was a load or store that suffered a translation miss",
+},
+[ POWER9_PME_PM_MRK_L2_RC_DONE ] = { /* 345 */
+	.pme_name = "PM_MRK_L2_RC_DONE",
+	.pme_code = 0x000003012A,
+	.pme_short_desc = "Marked RC done",
+	.pme_long_desc = "Marked RC done",
+},
+[ POWER9_PME_PM_INST_FROM_L3_1_SHR ] = { /* 346 */
+	.pme_name = "PM_INST_FROM_L3_1_SHR",
+	.pme_code = 0x0000014046,
+	.pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_RADIX_PWC_L4_PDE_FROM_L2 ] = { /* 347 */
+	.pme_name = "PM_RADIX_PWC_L4_PDE_FROM_L2",
+	.pme_code = 0x000002D02C,
+	.pme_short_desc = "A Page Directory Entry was reloaded to a level 4 page walk cache from the core's L2 data cache",
+	.pme_long_desc = "A Page Directory Entry was reloaded to a level 4 page walk cache from the core's L2 data cache",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L3_1_MOD ] = { /* 348 */
+	.pme_name = "PM_MRK_DATA_FROM_L3_1_MOD",
+	.pme_code = 0x000002D144,
+	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a marked load",
+},
+[ POWER9_PME_PM_CO0_BUSY ] = { /* 349 */
+	.pme_name = "PM_CO0_BUSY",
+	.pme_code = 0x000004608E,
+	.pme_short_desc = "CO mach 0 Busy.",
+	.pme_long_desc = "CO mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)",
+},
+[ POWER9_PME_PM_CMPLU_STALL_STORE_DATA ] = { /* 350 */
+	.pme_name = "PM_CMPLU_STALL_STORE_DATA",
+	.pme_code = 0x0000030026,
+	.pme_short_desc = "Finish stall because the next to finish instruction was a store waiting on data",
+	.pme_long_desc = "Finish stall because the next to finish instruction was a store waiting on data",
+},
+[ POWER9_PME_PM_INST_FROM_RMEM ] = { /* 351 */
+	.pme_name = "PM_INST_FROM_RMEM",
+	.pme_code = 0x000003404A,
+	.pme_short_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_SYNC_MRK_BR_LINK ] = { /* 352 */
+	.pme_name = "PM_SYNC_MRK_BR_LINK",
+	.pme_code = 0x0000015152,
+	.pme_short_desc = "Marked Branch and link branch that can cause a synchronous interrupt",
+	.pme_long_desc = "Marked Branch and link branch that can cause a synchronous interrupt",
+},
+[ POWER9_PME_PM_L3_LD_PREF ] = { /* 353 */
+	.pme_name = "PM_L3_LD_PREF",
+	.pme_code = 0x000000F0B0,
+	.pme_short_desc = "L3 load prefetch, sourced from a hardware or software stream, was sent to the nest",
+	.pme_long_desc = "L3 load prefetch, sourced from a hardware or software stream, was sent to the nest",
+},
+[ POWER9_PME_PM_DISP_CLB_HELD_TLBIE ] = { /* 354 */
+	.pme_name = "PM_DISP_CLB_HELD_TLBIE",
+	.pme_code = 0x0000002890,
+	.pme_short_desc = "Dispatch Hold: Due to TLBIE",
+	.pme_long_desc = "Dispatch Hold: Due to TLBIE",
+},
+[ POWER9_PME_PM_DPTEG_FROM_ON_CHIP_CACHE ] = { /* 355 */
+	.pme_name = "PM_DPTEG_FROM_ON_CHIP_CACHE",
+	.pme_code = 0x000001E048,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L3_MEPF_CYC ] = { /* 356 */
+	.pme_name = "PM_MRK_DATA_FROM_L3_MEPF_CYC",
+	.pme_code = 0x000001415C,
+	.pme_short_desc = "Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state.",
+	.pme_long_desc = "Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load",
+},
+[ POWER9_PME_PM_LS0_UNALIGNED_LD ] = { /* 357 */
+	.pme_name = "PM_LS0_UNALIGNED_LD",
+	.pme_code = 0x000000C094,
+	.pme_short_desc = "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size.",
+	.pme_long_desc = "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_DMEM_CYC ] = { /* 358 */
+	.pme_name = "PM_MRK_DATA_FROM_DMEM_CYC",
+	.pme_code = 0x000004E11E,
+	.pme_short_desc = "Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load",
+},
+[ POWER9_PME_PM_SN_HIT ] = { /* 359 */
+	.pme_name = "PM_SN_HIT",
+	.pme_code = 0x00000460A8,
+	.pme_short_desc = "Any port snooper hit.",
+	.pme_long_desc = "Any port snooper hit. Up to 4 can happen in a cycle but we only count 1",
+},
+[ POWER9_PME_PM_L3_LOC_GUESS_CORRECT ] = { /* 360 */
+	.pme_name = "PM_L3_LOC_GUESS_CORRECT",
+	.pme_code = 0x00000160B2,
+	.pme_short_desc = "initial scope=node/chip and data from local node (local) (pred successful)",
+	.pme_long_desc = "initial scope=node/chip and data from local node (local) (pred successful)",
+},
+[ POWER9_PME_PM_MRK_INST_FROM_L3MISS ] = { /* 361 */
+	.pme_name = "PM_MRK_INST_FROM_L3MISS",
+	.pme_code = 0x00000401E6,
+	.pme_short_desc = "Marked instruction was reloaded from a location beyond the local chiplet",
+	.pme_long_desc = "Marked instruction was reloaded from a location beyond the local chiplet",
+},
+[ POWER9_PME_PM_DECODE_FUSION_EXT_ADD ] = { /* 362 */
+	.pme_name = "PM_DECODE_FUSION_EXT_ADD",
+	.pme_code = 0x0000005084,
+	.pme_short_desc = "32-bit extended addition",
+	.pme_long_desc = "32-bit extended addition",
+},
+[ POWER9_PME_PM_INST_FROM_DL4 ] = { /* 363 */
+	.pme_name = "PM_INST_FROM_DL4",
+	.pme_code = 0x000003404C,
+	.pme_short_desc = "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_DC_PREF_XCONS_ALLOC ] = { /* 364 */
+	.pme_name = "PM_DC_PREF_XCONS_ALLOC",
+	.pme_code = 0x000000F8B4,
+	.pme_short_desc = "Prefetch stream allocated in the Ultra conservative phase by either the hardware prefetch mechanism or software prefetch",
+	.pme_long_desc = "Prefetch stream allocated in the Ultra conservative phase by either the hardware prefetch mechanism or software prefetch",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_MEMORY ] = { /* 365 */
+	.pme_name = "PM_MRK_DPTEG_FROM_MEMORY",
+	.pme_code = 0x000002F14C,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_IC_PREF_CANCEL_PAGE ] = { /* 366 */
+	.pme_name = "PM_IC_PREF_CANCEL_PAGE",
+	.pme_code = 0x0000004090,
+	.pme_short_desc = "Prefetch Canceled due to page boundary",
+	.pme_long_desc = "Prefetch Canceled due to page boundary",
+},
+[ POWER9_PME_PM_RADIX_PWC_L3_PTE_FROM_L3 ] = { /* 367 */
+	.pme_name = "PM_RADIX_PWC_L3_PTE_FROM_L3",
+	.pme_code = 0x000003F05E,
+	.pme_short_desc = "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache.",
+	.pme_long_desc = "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache. This implies that a level 4 PWC access was not necessary for this translation",
+},
+[ POWER9_PME_PM_L3_GRP_GUESS_WRONG_LOW ] = { /* 368 */
+	.pme_name = "PM_L3_GRP_GUESS_WRONG_LOW",
+	.pme_code = 0x00000360B2,
+	.pme_short_desc = "Initial scope=group but data from outside group (far or rem).",
+	.pme_long_desc = "Initial scope=group but data from outside group (far or rem). Prediction too Low",
+},
+[ POWER9_PME_PM_TM_FAIL_SELF ] = { /* 369 */
+	.pme_name = "PM_TM_FAIL_SELF",
+	.pme_code = 0x00000028AC,
+	.pme_short_desc = "TM aborted because a self-induced conflict occurred in Suspended state, due to one of the following: a store to a storage location that was previously accessed transactionally",
+	.pme_long_desc = "TM aborted because a self-induced conflict occurred in Suspended state, due to one of the following: a store to a storage location that was previously accessed transactionally",
+},
+[ POWER9_PME_PM_L3_P1_SYS_PUMP ] = { /* 370 */
+	.pme_name = "PM_L3_P1_SYS_PUMP",
+	.pme_code = 0x00000368B0,
+	.pme_short_desc = "L3 pf sent with sys scope port 1",
+	.pme_long_desc = "L3 pf sent with sys scope port 1",
+},
+[ POWER9_PME_PM_CMPLU_STALL_RFID ] = { /* 371 */
+	.pme_name = "PM_CMPLU_STALL_RFID",
+	.pme_code = 0x000002C01E,
+	.pme_short_desc = "Cycles in which the NTC instruction is not allowed to complete because it was interrupted by an RFID exception, which has to be serviced before the instruction can complete",
+	.pme_long_desc = "Cycles in which the NTC instruction is not allowed to complete because it was interrupted by an RFID exception, which has to be serviced before the instruction can complete",
+},
+[ POWER9_PME_PM_BR_2PATH ] = { /* 372 */
+	.pme_name = "PM_BR_2PATH",
+	.pme_code = 0x0000020036,
+	.pme_short_desc = "two path branch",
+	.pme_long_desc = "two path branch",
+},
+[ POWER9_PME_PM_RADIX_PWC_L4_PTE_FROM_L3MISS ] = { /* 373 */
+	.pme_name = "PM_RADIX_PWC_L4_PTE_FROM_L3MISS",
+	.pme_code = 0x000003F054,
+	.pme_short_desc = "A Page Table Entry was reloaded to a level 4 page walk cache from beyond the core's L3 data cache.",
+	.pme_long_desc = "A Page Table Entry was reloaded to a level 4 page walk cache from beyond the core's L3 data cache. This is the deepest level of PWC possible for a translation. The source could be local/remote/distant memory or another core's cache",
+},
+[ POWER9_PME_PM_DPTEG_FROM_L2MISS ] = { /* 374 */
+	.pme_name = "PM_DPTEG_FROM_L2MISS",
+	.pme_code = 0x000001E04E,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_TM_TX_PASS_RUN_INST ] = { /* 375 */
+	.pme_name = "PM_TM_TX_PASS_RUN_INST",
+	.pme_code = 0x000004E014,
+	.pme_short_desc = "Run instructions spent in successful transactions",
+	.pme_long_desc = "Run instructions spent in successful transactions",
+},
+[ POWER9_PME_PM_L1_ICACHE_RELOADED_PREF ] = { /* 376 */
+	.pme_name = "PM_L1_ICACHE_RELOADED_PREF",
+	.pme_code = 0x0000030068,
+	.pme_short_desc = "Counts all Icache prefetch reloads ( includes demand turned into prefetch)",
+	.pme_long_desc = "Counts all Icache prefetch reloads ( includes demand turned into prefetch)",
+},
+[ POWER9_PME_PM_THRESH_EXC_4096 ] = { /* 377 */
+	.pme_name = "PM_THRESH_EXC_4096",
+	.pme_code = 0x00000101E6,
+	.pme_short_desc = "Threshold counter exceed a count of 4096",
+	.pme_long_desc = "Threshold counter exceed a count of 4096",
+},
+[ POWER9_PME_PM_IERAT_RELOAD_64K ] = { /* 378 */
+	.pme_name = "PM_IERAT_RELOAD_64K",
+	.pme_code = 0x000003006A,
+	.pme_short_desc = "IERAT Reloaded (Miss) for a 64k page",
+	.pme_long_desc = "IERAT Reloaded (Miss) for a 64k page",
+},
+[ POWER9_PME_PM_LSU0_TM_L1_MISS ] = { /* 379 */
+	.pme_name = "PM_LSU0_TM_L1_MISS",
+	.pme_code = 0x000000E09C,
+	.pme_short_desc = "Load tm L1 miss",
+	.pme_long_desc = "Load tm L1 miss",
+},
+[ POWER9_PME_PM_MEM_LOC_THRESH_LSU_MED ] = { /* 380 */
+	.pme_name = "PM_MEM_LOC_THRESH_LSU_MED",
+	.pme_code = 0x000001C05E,
+	.pme_short_desc = "Local memory above theshold for data prefetch",
+	.pme_long_desc = "Local memory above theshold for data prefetch",
+},
+[ POWER9_PME_PM_PMC3_REWIND ] = { /* 381 */
+	.pme_name = "PM_PMC3_REWIND",
+	.pme_code = 0x000001000A,
+	.pme_short_desc = "PMC3 rewind event.",
+	.pme_long_desc = "PMC3 rewind event. A rewind happens when a speculative event (such as latency or CPI stack) is selected on PMC3 and the stall reason or reload source did not match the one programmed in PMC3. When this occurs, the count in PMC3 will not change.",
+},
+[ POWER9_PME_PM_ST_FWD ] = { /* 382 */
+	.pme_name = "PM_ST_FWD",
+	.pme_code = 0x0000020018,
+	.pme_short_desc = "Store forwards that finished",
+	.pme_long_desc = "Store forwards that finished",
+},
+[ POWER9_PME_PM_TM_FAIL_TX_CONFLICT ] = { /* 383 */
+	.pme_name = "PM_TM_FAIL_TX_CONFLICT",
+	.pme_code = 0x000000E8AC,
+	.pme_short_desc = "Transactional conflict from LSU, whatever gets reported to texas",
+	.pme_long_desc = "Transactional conflict from LSU, whatever gets reported to texas",
+},
+[ POWER9_PME_PM_SYNC_MRK_L2MISS ] = { /* 384 */
+	.pme_name = "PM_SYNC_MRK_L2MISS",
+	.pme_code = 0x000001515A,
+	.pme_short_desc = "Marked L2 Miss that can throw a synchronous interrupt",
+	.pme_long_desc = "Marked L2 Miss that can throw a synchronous interrupt",
+},
+[ POWER9_PME_PM_ISU0_ISS_HOLD_ALL ] = { /* 385 */
+	.pme_name = "PM_ISU0_ISS_HOLD_ALL",
+	.pme_code = 0x0000003080,
+	.pme_short_desc = "All ISU rejects",
+	.pme_long_desc = "All ISU rejects",
+},
+[ POWER9_PME_PM_MRK_FAB_RSP_DCLAIM_CYC ] = { /* 386 */
+	.pme_name = "PM_MRK_FAB_RSP_DCLAIM_CYC",
+	.pme_code = 0x000002F152,
+	.pme_short_desc = "cycles L2 RC took for a dclaim",
+	.pme_long_desc = "cycles L2 RC took for a dclaim",
+},
+[ POWER9_PME_PM_DATA_FROM_L2 ] = { /* 387 */
+	.pme_name = "PM_DATA_FROM_L2",
+	.pme_code = 0x000001C042,
+	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 due to a demand load",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_RL2L3_MOD ] = { /* 388 */
+	.pme_name = "PM_MRK_DATA_FROM_RL2L3_MOD",
+	.pme_code = 0x000001D14A,
+	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
+},
+[ POWER9_PME_PM_ISQ_0_8_ENTRIES ] = { /* 389 */
+	.pme_name = "PM_ISQ_0_8_ENTRIES",
+	.pme_code = 0x000003005A,
+	.pme_short_desc = "Cycles in which 8 or less Issue Queue entries are in use.",
+	.pme_long_desc = "Cycles in which 8 or less Issue Queue entries are in use. This is a shared event, not per thread",
+},
+[ POWER9_PME_PM_L3_CO_MEPF ] = { /* 390 */
+	.pme_name = "PM_L3_CO_MEPF",
+	.pme_code = 0x00000168A0,
+	.pme_short_desc = "L3 CO of line in Mep state ( includes casthrough",
+	.pme_long_desc = "L3 CO of line in Mep state ( includes casthrough",
+},
+[ POWER9_PME_PM_LINK_STACK_INVALID_PTR ] = { /* 391 */
+	.pme_name = "PM_LINK_STACK_INVALID_PTR",
+	.pme_code = 0x0000005898,
+	.pme_short_desc = "It is most often caused by certain types of flush where the pointer is not available.",
+	.pme_long_desc = "It is most often caused by certain types of flush where the pointer is not available. Can result in the data in the link stack becoming unusable.",
+},
+[ POWER9_PME_PM_IPTEG_FROM_L2_1_MOD ] = { /* 392 */
+	.pme_name = "PM_IPTEG_FROM_L2_1_MOD",
+	.pme_code = 0x0000045046,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a instruction side request",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a instruction side request",
+},
+[ POWER9_PME_PM_TM_ST_CAUSED_FAIL ] = { /* 393 */
+	.pme_name = "PM_TM_ST_CAUSED_FAIL",
+	.pme_code = 0x000003688C,
+	.pme_short_desc = "TM Store (fav or non-fav) caused another thread to fail",
+	.pme_long_desc = "TM Store (fav or non-fav) caused another thread to fail",
+},
+[ POWER9_PME_PM_LD_REF_L1 ] = { /* 394 */
+	.pme_name = "PM_LD_REF_L1",
+	.pme_code = 0x00000100FC,
+	.pme_short_desc = "All L1 D cache load references counted at finish, gated by reject",
+	.pme_long_desc = "All L1 D cache load references counted at finish, gated by reject",
+},
+[ POWER9_PME_PM_TM_FAIL_NON_TX_CONFLICT ] = { /* 395 */
+	.pme_name = "PM_TM_FAIL_NON_TX_CONFLICT",
+	.pme_code = 0x000000E0B0,
+	.pme_short_desc = "Non transactional conflict from LSU whtver gets repoted to texas",
+	.pme_long_desc = "Non transactional conflict from LSU whtver gets repoted to texas",
+},
+[ POWER9_PME_PM_GRP_PUMP_CPRED ] = { /* 396 */
+	.pme_name = "PM_GRP_PUMP_CPRED",
+	.pme_code = 0x0000020050,
+	.pme_short_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
+	.pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
+},
+[ POWER9_PME_PM_INST_FROM_L3_NO_CONFLICT ] = { /* 397 */
+	.pme_name = "PM_INST_FROM_L3_NO_CONFLICT",
+	.pme_code = 0x0000014044,
+	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 without conflict due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 without conflict due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_DC_PREF_STRIDED_CONF ] = { /* 398 */
+	.pme_name = "PM_DC_PREF_STRIDED_CONF",
+	.pme_code = 0x000000F0AC,
+	.pme_short_desc = "A demand load referenced a line in an active strided prefetch stream.",
+	.pme_long_desc = "A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.",
+},
+[ POWER9_PME_PM_THRD_PRIO_6_7_CYC ] = { /* 399 */
+	.pme_name = "PM_THRD_PRIO_6_7_CYC",
+	.pme_code = 0x0000005880,
+	.pme_short_desc = "Cycles thread running at priority level 6 or 7",
+	.pme_long_desc = "Cycles thread running at priority level 6 or 7",
+},
+[ POWER9_PME_PM_RADIX_PWC_L4_PDE_FROM_L3 ] = { /* 400 */
+	.pme_name = "PM_RADIX_PWC_L4_PDE_FROM_L3",
+	.pme_code = 0x000003F05C,
+	.pme_short_desc = "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L3 data cache",
+	.pme_long_desc = "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L3 data cache",
+},
+[ POWER9_PME_PM_L3_PF_OFF_CHIP_MEM ] = { /* 401 */
+	.pme_name = "PM_L3_PF_OFF_CHIP_MEM",
+	.pme_code = 0x00000468A0,
+	.pme_short_desc = "L3 Prefetch from Off chip memory",
+	.pme_long_desc = "L3 Prefetch from Off chip memory",
+},
+[ POWER9_PME_PM_L3_CO_MEM ] = { /* 402 */
+	.pme_name = "PM_L3_CO_MEM",
+	.pme_code = 0x00000260A0,
+	.pme_short_desc = "L3 CO to memory OR of port 0 and 1 ( lossy)",
+	.pme_long_desc = "L3 CO to memory OR of port 0 and 1 ( lossy)",
+},
+[ POWER9_PME_PM_DECODE_HOLD_ICT_FULL ] = { /* 403 */
+	.pme_name = "PM_DECODE_HOLD_ICT_FULL",
+	.pme_code = 0x00000058A8,
+	.pme_short_desc = "Counts the number of cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use.",
+	.pme_long_desc = "Counts the number of cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use. This means the ICT is full for this thread",
+},
+[ POWER9_PME_PM_CMPLU_STALL_DFLONG ] = { /* 404 */
+	.pme_name = "PM_CMPLU_STALL_DFLONG",
+	.pme_code = 0x000001005A,
+	.pme_short_desc = "Finish stall because the NTF instruction was a multi-cycle instruction issued to the Decimal Floating Point execution pipe and waiting to finish.",
+	.pme_long_desc = "Finish stall because the NTF instruction was a multi-cycle instruction issued to the Decimal Floating Point execution pipe and waiting to finish. Includes decimal floating point instructions + 128 bit binary floating point instructions. Qualified by multicycle",
+},
+[ POWER9_PME_PM_LD_MISS_L1 ] = { /* 405 */
+	.pme_name = "PM_LD_MISS_L1",
+	.pme_code = 0x000003E054,
+	.pme_short_desc = "Load Missed L1, at execution time (not gated by finish, which means this counter can be greater than loads finished)",
+	.pme_long_desc = "Load Missed L1, at execution time (not gated by finish, which means this counter can be greater than loads finished)",
+},
+[ POWER9_PME_PM_DATA_FROM_RL2L3_MOD ] = { /* 406 */
+	.pme_name = "PM_DATA_FROM_RL2L3_MOD",
+	.pme_code = 0x000002C046,
+	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load",
+},
+[ POWER9_PME_PM_L3_WI0_BUSY ] = { /* 407 */
+	.pme_name = "PM_L3_WI0_BUSY",
+	.pme_code = 0x00000260B6,
+	.pme_short_desc = "lifetime, sample of Write Inject machine 0 valid",
+	.pme_long_desc = "lifetime, sample of Write Inject machine 0 valid",
+},
+[ POWER9_PME_PM_LSU_SRQ_FULL_CYC ] = { /* 408 */
+	.pme_name = "PM_LSU_SRQ_FULL_CYC",
+	.pme_code = 0x000001001A,
+	.pme_short_desc = "Cycles in which the Store Queue is full on all 4 slices.",
+	.pme_long_desc = "Cycles in which the Store Queue is full on all 4 slices. This is event is not per thread. All the threads will see the same count for this core resource",
+},
+[ POWER9_PME_PM_TABLEWALK_CYC ] = { /* 409 */
+	.pme_name = "PM_TABLEWALK_CYC",
+	.pme_code = 0x0000010026,
+	.pme_short_desc = "Cycles when a tablewalk (I or D) is active",
+	.pme_long_desc = "Cycles when a tablewalk (I or D) is active",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_MEMORY_CYC ] = { /* 410 */
+	.pme_name = "PM_MRK_DATA_FROM_MEMORY_CYC",
+	.pme_code = 0x000001D146,
+	.pme_short_desc = "Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load",
+},
+[ POWER9_PME_PM_IPTEG_FROM_OFF_CHIP_CACHE ] = { /* 411 */
+	.pme_name = "PM_IPTEG_FROM_OFF_CHIP_CACHE",
+	.pme_code = 0x000004504A,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request",
+},
+[ POWER9_PME_PM_RADIX_PWC_L1_PDE_FROM_L3MISS ] = { /* 412 */
+	.pme_name = "PM_RADIX_PWC_L1_PDE_FROM_L3MISS",
+	.pme_code = 0x000004F056,
+	.pme_short_desc = "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond the core's L3 data cache.",
+	.pme_long_desc = "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond the core's L3 data cache. The source could be local/remote/distant memory or another core's cache",
+},
+[ POWER9_PME_PM_CMPLU_STALL_SYS_CALL ] = { /* 413 */
+	.pme_name = "PM_CMPLU_STALL_SYS_CALL",
+	.pme_code = 0x000001E05A,
+	.pme_short_desc = "Cycles in which the NTC instruction is not allowed to complete because it was interrupted by a system call exception, which has to be serviced before the instruction can complete",
+	.pme_long_desc = "Cycles in which the NTC instruction is not allowed to complete because it was interrupted by a system call exception, which has to be serviced before the instruction can complete",
+},
+[ POWER9_PME_PM_LSU_FLUSH_RELAUNCH_MISS ] = { /* 414 */
+	.pme_name = "PM_LSU_FLUSH_RELAUNCH_MISS",
+	.pme_code = 0x000000C8B0,
+	.pme_short_desc = "If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent",
+	.pme_long_desc = "If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent",
+},
+[ POWER9_PME_PM_DPTEG_FROM_L3_1_ECO_MOD ] = { /* 415 */
+	.pme_name = "PM_DPTEG_FROM_L3_1_ECO_MOD",
+	.pme_code = 0x000004E044,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_PMC5_OVERFLOW ] = { /* 416 */
+	.pme_name = "PM_PMC5_OVERFLOW",
+	.pme_code = 0x0000010024,
+	.pme_short_desc = "Overflow from counter 5",
+	.pme_long_desc = "Overflow from counter 5",
+},
+[ POWER9_PME_PM_LS1_UNALIGNED_ST ] = { /* 417 */
+	.pme_name = "PM_LS1_UNALIGNED_ST",
+	.pme_code = 0x000000F8B8,
+	.pme_short_desc = "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size.",
+	.pme_long_desc = "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty",
+},
+[ POWER9_PME_PM_ICT_NOSLOT_DISP_HELD_SYNC ] = { /* 418 */
+	.pme_name = "PM_ICT_NOSLOT_DISP_HELD_SYNC",
+	.pme_code = 0x000004D01C,
+	.pme_short_desc = "Dispatch held due to a synchronizing instruction at dispatch",
+	.pme_long_desc = "Dispatch held due to a synchronizing instruction at dispatch",
+},
+[ POWER9_PME_PM_CMPLU_STALL_THRD ] = { /* 419 */
+	.pme_name = "PM_CMPLU_STALL_THRD",
+	.pme_code = 0x000001001C,
+	.pme_short_desc = "Completion Stalled because the thread was blocked",
+	.pme_long_desc = "Completion Stalled because the thread was blocked",
+},
+[ POWER9_PME_PM_PMC3_SAVED ] = { /* 420 */
+	.pme_name = "PM_PMC3_SAVED",
+	.pme_code = 0x000004D012,
+	.pme_short_desc = "PMC3 Rewind Value saved",
+	.pme_long_desc = "PMC3 Rewind Value saved",
+},
+[ POWER9_PME_PM_MRK_DERAT_MISS ] = { /* 421 */
+	.pme_name = "PM_MRK_DERAT_MISS",
+	.pme_code = 0x00000301E6,
+	.pme_short_desc = "Erat Miss (TLB Access) All page sizes",
+	.pme_long_desc = "Erat Miss (TLB Access) All page sizes",
+},
+[ POWER9_PME_PM_RADIX_PWC_L3_HIT ] = { /* 422 */
+	.pme_name = "PM_RADIX_PWC_L3_HIT",
+	.pme_code = 0x000003F056,
+	.pme_short_desc = "A radix translation attempt missed in the TLB but hit on the first, second, and third levels of page walk cache.",
+	.pme_long_desc = "A radix translation attempt missed in the TLB but hit on the first, second, and third levels of page walk cache.",
+},
+[ POWER9_PME_PM_RADIX_PWC_L2_PTE_FROM_L3MISS ] = { /* 423 */
+	.pme_name = "PM_RADIX_PWC_L2_PTE_FROM_L3MISS",
+	.pme_code = 0x000004F05C,
+	.pme_short_desc = "A Page Table Entry was reloaded to a level 2 page walk cache from beyond the core's L3 data cache.",
+	.pme_long_desc = "A Page Table Entry was reloaded to a level 2 page walk cache from beyond the core's L3 data cache. This implies that level 3 and level 4 PWC accesses were not necessary for this translation. The source could be local/remote/distant memory or another core's cache",
+},
+[ POWER9_PME_PM_RUN_CYC_SMT4_MODE ] = { /* 424 */
+	.pme_name = "PM_RUN_CYC_SMT4_MODE",
+	.pme_code = 0x000002006C,
+	.pme_short_desc = "Cycles in which this thread's run latch is set and the core is in SMT4 mode",
+	.pme_long_desc = "Cycles in which this thread's run latch is set and the core is in SMT4 mode",
+},
+[ POWER9_PME_PM_DATA_FROM_RMEM ] = { /* 425 */
+	.pme_name = "PM_DATA_FROM_RMEM",
+	.pme_code = 0x000003C04A,
+	.pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load",
+},
+[ POWER9_PME_PM_BR_MPRED_LSTACK ] = { /* 426 */
+	.pme_name = "PM_BR_MPRED_LSTACK",
+	.pme_code = 0x00000048AC,
+	.pme_short_desc = "Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction",
+	.pme_long_desc = "Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction",
+},
+[ POWER9_PME_PM_PROBE_NOP_DISP ] = { /* 427 */
+	.pme_name = "PM_PROBE_NOP_DISP",
+	.pme_code = 0x0000040014,
+	.pme_short_desc = "ProbeNops dispatched",
+	.pme_long_desc = "ProbeNops dispatched",
+},
+[ POWER9_PME_PM_DPTEG_FROM_L3_MEPF ] = { /* 428 */
+	.pme_name = "PM_DPTEG_FROM_L3_MEPF",
+	.pme_code = 0x000002E042,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_INST_FROM_L3MISS_MOD ] = { /* 429 */
+	.pme_name = "PM_INST_FROM_L3MISS_MOD",
+	.pme_code = 0x000004404E,
+	.pme_short_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to a instruction fetch",
+	.pme_long_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to a instruction fetch",
+},
+[ POWER9_PME_PM_DUMMY1_REMOVE_ME ] = { /* 430 */
+	.pme_name = "PM_DUMMY1_REMOVE_ME",
+	.pme_code = 0x0000040062,
+	.pme_short_desc = "Space holder for l2_pc_pm_mk_ldst_scope_pred_status",
+	.pme_long_desc = "Space holder for l2_pc_pm_mk_ldst_scope_pred_status",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_DL4 ] = { /* 431 */
+	.pme_name = "PM_MRK_DATA_FROM_DL4",
+	.pme_code = 0x000001D152,
+	.pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_RL2L3_MOD_CYC ] = { /* 432 */
+	.pme_name = "PM_MRK_DATA_FROM_RL2L3_MOD_CYC",
+	.pme_code = 0x000002D14A,
+	.pme_short_desc = "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
+},
+[ POWER9_PME_PM_IPTEG_FROM_L3_1_SHR ] = { /* 433 */
+	.pme_name = "PM_IPTEG_FROM_L3_1_SHR",
+	.pme_code = 0x0000015046,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L3_1_ECO_SHR ] = { /* 434 */
+	.pme_name = "PM_MRK_DATA_FROM_L3_1_ECO_SHR",
+	.pme_code = 0x000002D14C,
+	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load",
+},
+[ POWER9_PME_PM_DTLB_MISS_2M ] = { /* 435 */
+	.pme_name = "PM_DTLB_MISS_2M",
+	.pme_code = 0x000001C05C,
+	.pme_short_desc = "Data TLB reload (after a miss) page size 2M.",
+	.pme_long_desc = "Data TLB reload (after a miss) page size 2M. Implies radix translation was used",
+},
+[ POWER9_PME_PM_TM_RST_SC ] = { /* 436 */
+	.pme_name = "PM_TM_RST_SC",
+	.pme_code = 0x00000268A6,
+	.pme_short_desc = "tm snp rst tm sc",
+	.pme_long_desc = "tm snp rst tm sc",
+},
+[ POWER9_PME_PM_LSU_NCST ] = { /* 437 */
+	.pme_name = "PM_LSU_NCST",
+	.pme_code = 0x000000C890,
+	.pme_short_desc = "Asserts when a i=1 store op is sent to the nest.",
+	.pme_long_desc = "Asserts when a i=1 store op is sent to the nest. No record of issue pipe (LS0/LS1) is maintained so this is for both pipes. Probably don't need separate LS0 and LS1",
+},
+[ POWER9_PME_PM_DATA_SYS_PUMP_MPRED_RTY ] = { /* 438 */
+	.pme_name = "PM_DATA_SYS_PUMP_MPRED_RTY",
+	.pme_code = 0x000004C050,
+	.pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a demand load",
+	.pme_long_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a demand load",
+},
+[ POWER9_PME_PM_THRESH_ACC ] = { /* 439 */
+	.pme_name = "PM_THRESH_ACC",
+	.pme_code = 0x0000024154,
+	.pme_short_desc = "This event increments every time the threshold event counter ticks.",
+	.pme_long_desc = "This event increments every time the threshold event counter ticks. Thresholding must be enabled (via MMCRA) and the thresholding start event must occur for this counter to increment. It will stop incrementing when the thresholding stop event occurs or when thresholding is disabled, until the next time a configured thresholding start event occurs.",
+},
+[ POWER9_PME_PM_ISU3_ISS_HOLD_ALL ] = { /* 440 */
+	.pme_name = "PM_ISU3_ISS_HOLD_ALL",
+	.pme_code = 0x0000003884,
+	.pme_short_desc = "All ISU rejects",
+	.pme_long_desc = "All ISU rejects",
+},
+[ POWER9_PME_PM_LSU0_L1_CAM_CANCEL ] = { /* 441 */
+	.pme_name = "PM_LSU0_L1_CAM_CANCEL",
+	.pme_code = 0x000000F090,
+	.pme_short_desc = "ls0 l1 tm cam cancel",
+	.pme_long_desc = "ls0 l1 tm cam cancel",
+},
+[ POWER9_PME_PM_MRK_FAB_RSP_BKILL_CYC ] = { /* 442 */
+	.pme_name = "PM_MRK_FAB_RSP_BKILL_CYC",
+	.pme_code = 0x000001F152,
+	.pme_short_desc = "cycles L2 RC took for a bkill",
+	.pme_long_desc = "cycles L2 RC took for a bkill",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_L3_MEPF ] = { /* 443 */
+	.pme_name = "PM_MRK_DPTEG_FROM_L3_MEPF",
+	.pme_code = 0x000002F142,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_DARQ_STORE_REJECT ] = { /* 444 */
+	.pme_name = "PM_DARQ_STORE_REJECT",
+	.pme_code = 0x000004405E,
+	.pme_short_desc = "The DARQ attempted to transmit a store into an LSAQ or SRQ entry but It was rejected.",
+	.pme_long_desc = "The DARQ attempted to transmit a store into an LSAQ or SRQ entry but It was rejected. Divide by pm_darq_store_xmit to get reject ratio",
+},
+[ POWER9_PME_PM_DPTEG_FROM_L3_NO_CONFLICT ] = { /* 445 */
+	.pme_name = "PM_DPTEG_FROM_L3_NO_CONFLICT",
+	.pme_code = 0x000001E044,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_TM_TX_PASS_RUN_CYC ] = { /* 446 */
+	.pme_name = "PM_TM_TX_PASS_RUN_CYC",
+	.pme_code = 0x000002E012,
+	.pme_short_desc = "cycles spent in successful transactions",
+	.pme_long_desc = "cycles spent in successful transactions",
+},
+[ POWER9_PME_PM_DTLB_MISS_4K ] = { /* 447 */
+	.pme_name = "PM_DTLB_MISS_4K",
+	.pme_code = 0x000002C056,
+	.pme_short_desc = "Data TLB Miss page size 4k",
+	.pme_long_desc = "Data TLB Miss page size 4k",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC ] = { /* 448 */
+	.pme_name = "PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC",
+	.pme_code = 0x000003515A,
+	.pme_short_desc = "Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load",
+},
+[ POWER9_PME_PM_LS0_PTE_TABLEWALK_CYC ] = { /* 449 */
+	.pme_name = "PM_LS0_PTE_TABLEWALK_CYC",
+	.pme_code = 0x000000E0BC,
+	.pme_short_desc = "Cycles when a tablewalk is pending on this thread on table 0",
+	.pme_long_desc = "Cycles when a tablewalk is pending on this thread on table 0",
+},
+[ POWER9_PME_PM_PMC4_SAVED ] = { /* 450 */
+	.pme_name = "PM_PMC4_SAVED",
+	.pme_code = 0x0000030022,
+	.pme_short_desc = "PMC4 Rewind Value saved (matched condition)",
+	.pme_long_desc = "PMC4 Rewind Value saved (matched condition)",
+},
+[ POWER9_PME_PM_SNP_TM_HIT_T ] = { /* 451 */
+	.pme_name = "PM_SNP_TM_HIT_T",
+	.pme_code = 0x00000368A6,
+	.pme_short_desc = "snp tm_st_hit t tn te",
+	.pme_long_desc = "snp tm_st_hit t tn te",
+},
+[ POWER9_PME_PM_MRK_BR_2PATH ] = { /* 452 */
+	.pme_name = "PM_MRK_BR_2PATH",
+	.pme_code = 0x0000010138,
+	.pme_short_desc = "marked two path branch",
+	.pme_long_desc = "marked two path branch",
+},
+[ POWER9_PME_PM_LSU_FLUSH_CI ] = { /* 453 */
+	.pme_name = "PM_LSU_FLUSH_CI",
+	.pme_code = 0x000000C0A8,
+	.pme_short_desc = "Load was not issued to LSU as a cache inhibited (non-cacheable) load but it was later determined to be cache inhibited",
+	.pme_long_desc = "Load was not issued to LSU as a cache inhibited (non-cacheable) load but it was later determined to be cache inhibited",
+},
+[ POWER9_PME_PM_FLUSH_MPRED ] = { /* 454 */
+	.pme_name = "PM_FLUSH_MPRED",
+	.pme_code = 0x00000050A4,
+	.pme_short_desc = "Branch mispredict flushes.",
+	.pme_long_desc = "Branch mispredict flushes. Includes target and address misprecition",
+},
+[ POWER9_PME_PM_CMPLU_STALL_ST_FWD ] = { /* 455 */
+	.pme_name = "PM_CMPLU_STALL_ST_FWD",
+	.pme_code = 0x000004C01C,
+	.pme_short_desc = "Completion stall due to store forward",
+	.pme_long_desc = "Completion stall due to store forward",
+},
+[ POWER9_PME_PM_DTLB_MISS ] = { /* 456 */
+	.pme_name = "PM_DTLB_MISS",
+	.pme_code = 0x00000300FC,
+	.pme_short_desc = "Data PTEG reload",
+	.pme_long_desc = "Data PTEG reload",
+},
+[ POWER9_PME_PM_MRK_L2_TM_REQ_ABORT ] = { /* 457 */
+	.pme_name = "PM_MRK_L2_TM_REQ_ABORT",
+	.pme_code = 0x000001E15E,
+	.pme_short_desc = "TM abort",
+	.pme_long_desc = "TM abort",
+},
+[ POWER9_PME_PM_TM_NESTED_TEND ] = { /* 458 */
+	.pme_name = "PM_TM_NESTED_TEND",
+	.pme_code = 0x0000002098,
+	.pme_short_desc = "Completion time nested tend",
+	.pme_long_desc = "Completion time nested tend",
+},
+[ POWER9_PME_PM_CMPLU_STALL_PM ] = { /* 459 */
+	.pme_name = "PM_CMPLU_STALL_PM",
+	.pme_code = 0x000003000A,
+	.pme_short_desc = "Finish stall because the NTF instruction was issued to the Permute execution pipe and waiting to finish.",
+	.pme_long_desc = "Finish stall because the NTF instruction was issued to the Permute execution pipe and waiting to finish. Includes permute and decimal fixpoint instructions (128 bit BCD arithmetic) + a few 128 bit fixpoint add/subtract instructions with carry. Not qualified by vector or multicycle",
+},
+[ POWER9_PME_PM_CMPLU_STALL_ISYNC ] = { /* 460 */
+	.pme_name = "PM_CMPLU_STALL_ISYNC",
+	.pme_code = 0x000003002E,
+	.pme_short_desc = "Completion stall because the ISU is checking the scoreboard for whether the isync instruction requires a flush or not",
+	.pme_long_desc = "Completion stall because the ISU is checking the scoreboard for whether the isync instruction requires a flush or not",
+},
+[ POWER9_PME_PM_MRK_DTLB_MISS_1G ] = { /* 461 */
+	.pme_name = "PM_MRK_DTLB_MISS_1G",
+	.pme_code = 0x000001D15C,
+	.pme_short_desc = "Marked Data TLB reload (after a miss) page size 2M.",
+	.pme_long_desc = "Marked Data TLB reload (after a miss) page size 2M. Implies radix translation was used",
+},
+[ POWER9_PME_PM_L3_SYS_GUESS_CORRECT ] = { /* 462 */
+	.pme_name = "PM_L3_SYS_GUESS_CORRECT",
+	.pme_code = 0x00000260B2,
+	.pme_short_desc = "Initial scope=system and data from outside group (far or rem)(pred successful)",
+	.pme_long_desc = "Initial scope=system and data from outside group (far or rem)(pred successful)",
+},
+[ POWER9_PME_PM_L2_CASTOUT_SHR ] = { /* 463 */
+	.pme_name = "PM_L2_CASTOUT_SHR",
+	.pme_code = 0x0000016882,
+	.pme_short_desc = "L2 Castouts - Shared (T, Te, Si, S)",
+	.pme_long_desc = "L2 Castouts - Shared (T, Te, Si, S)",
+},
+[ POWER9_PME_PM_CMPLU_STALL_DMISS_L2L3 ] = { /* 464 */
+	.pme_name = "PM_CMPLU_STALL_DMISS_L2L3",
+	.pme_code = 0x000001003C,
+	.pme_short_desc = "Completion stall by Dcache miss which resolved in L2/L3",
+	.pme_long_desc = "Completion stall by Dcache miss which resolved in L2/L3",
+},
+[ POWER9_PME_PM_LS2_UNALIGNED_ST ] = { /* 465 */
+	.pme_name = "PM_LS2_UNALIGNED_ST",
+	.pme_code = 0x000000F0BC,
+	.pme_short_desc = "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size.",
+	.pme_long_desc = "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_L2MISS ] = { /* 466 */
+	.pme_name = "PM_MRK_DPTEG_FROM_L2MISS",
+	.pme_code = 0x000001F14E,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a marked data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_THRESH_EXC_32 ] = { /* 467 */
+	.pme_name = "PM_THRESH_EXC_32",
+	.pme_code = 0x00000201E6,
+	.pme_short_desc = "Threshold counter exceeded a value of 32",
+	.pme_long_desc = "Threshold counter exceeded a value of 32",
+},
+[ POWER9_PME_PM_TM_TSUSPEND ] = { /* 468 */
+	.pme_name = "PM_TM_TSUSPEND",
+	.pme_code = 0x00000028A0,
+	.pme_short_desc = "TM suspend instruction completed",
+	.pme_long_desc = "TM suspend instruction completed",
+},
+[ POWER9_PME_PM_DATA_FROM_DL2L3_SHR ] = { /* 469 */
+	.pme_name = "PM_DATA_FROM_DL2L3_SHR",
+	.pme_code = 0x000003C048,
+	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L3_DISP_CONFLICT ] = { /* 470 */
+	.pme_name = "PM_MRK_DATA_FROM_L3_DISP_CONFLICT",
+	.pme_code = 0x000001D144,
+	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L3_1_ECO_SHR_CYC ] = { /* 471 */
+	.pme_name = "PM_MRK_DATA_FROM_L3_1_ECO_SHR_CYC",
+	.pme_code = 0x000001D142,
+	.pme_short_desc = "Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load",
+},
+[ POWER9_PME_PM_THRESH_EXC_1024 ] = { /* 472 */
+	.pme_name = "PM_THRESH_EXC_1024",
+	.pme_code = 0x00000301EA,
+	.pme_short_desc = "Threshold counter exceeded a value of 1024",
+	.pme_long_desc = "Threshold counter exceeded a value of 1024",
+},
+[ POWER9_PME_PM_ST_FIN ] = { /* 473 */
+	.pme_name = "PM_ST_FIN",
+	.pme_code = 0x0000020016,
+	.pme_short_desc = "Store finish count.",
+	.pme_long_desc = "Store finish count. Includes speculative activity",
+},
+[ POWER9_PME_PM_TM_LD_CAUSED_FAIL ] = { /* 474 */
+	.pme_name = "PM_TM_LD_CAUSED_FAIL",
+	.pme_code = 0x000001688C,
+	.pme_short_desc = "Non TM Ld caused any thread to fail",
+	.pme_long_desc = "Non TM Ld caused any thread to fail",
+},
+[ POWER9_PME_PM_SRQ_SYNC_CYC ] = { /* 475 */
+	.pme_name = "PM_SRQ_SYNC_CYC",
+	.pme_code = 0x000000D0AC,
+	.pme_short_desc = "A sync is in the S2Q (edge detect to count)",
+	.pme_long_desc = "A sync is in the S2Q (edge detect to count)",
+},
+[ POWER9_PME_PM_IFETCH_THROTTLE ] = { /* 476 */
+	.pme_name = "PM_IFETCH_THROTTLE",
+	.pme_code = 0x000003405E,
+	.pme_short_desc = "Cycles in which Instruction fetch throttle was active.",
+	.pme_long_desc = "Cycles in which Instruction fetch throttle was active.",
+},
+[ POWER9_PME_PM_L3_SW_PREF ] = { /* 477 */
+	.pme_name = "PM_L3_SW_PREF",
+	.pme_code = 0x000000F8B0,
+	.pme_short_desc = "L3 load prefetch, sourced from a software prefetch stream, was sent to the nest",
+	.pme_long_desc = "L3 load prefetch, sourced from a software prefetch stream, was sent to the nest",
+},
+[ POWER9_PME_PM_LSU0_LDMX_FIN ] = { /* 478 */
+	.pme_name = "PM_LSU0_LDMX_FIN",
+	.pme_code = 0x000000D088,
+	.pme_short_desc = " New P9 instruction LDMX.",
+	.pme_long_desc = " New P9 instruction LDMX.",
+},
+[ POWER9_PME_PM_L2_LOC_GUESS_WRONG ] = { /* 479 */
+	.pme_name = "PM_L2_LOC_GUESS_WRONG",
+	.pme_code = 0x0000016888,
+	.pme_short_desc = "L2 guess loc and guess was not correct (ie data not on chip)",
+	.pme_long_desc = "L2 guess loc and guess was not correct (ie data not on chip)",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC ] = { /* 480 */
+	.pme_name = "PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC",
+	.pme_code = 0x0000014158,
+	.pme_short_desc = "Duration in cycles to reload from local core's L2 without conflict due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload from local core's L2 without conflict due to a marked load",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_ON_CHIP_CACHE ] = { /* 481 */
+	.pme_name = "PM_MRK_DPTEG_FROM_ON_CHIP_CACHE",
+	.pme_code = 0x000001F148,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_L3_P1_CO_RTY ] = { /* 482 */
+	.pme_name = "PM_L3_P1_CO_RTY",
+	.pme_code = 0x00000468AE,
+	.pme_short_desc = "L3 CO received retry port 3",
+	.pme_long_desc = "L3 CO received retry port 3",
+},
+[ POWER9_PME_PM_MRK_STCX_FAIL ] = { /* 483 */
+	.pme_name = "PM_MRK_STCX_FAIL",
+	.pme_code = 0x000003E158,
+	.pme_short_desc = "marked stcx failed",
+	.pme_long_desc = "marked stcx failed",
+},
+[ POWER9_PME_PM_LARX_FIN ] = { /* 484 */
+	.pme_name = "PM_LARX_FIN",
+	.pme_code = 0x000003C058,
+	.pme_short_desc = "Larx finished",
+	.pme_long_desc = "Larx finished",
+},
+[ POWER9_PME_PM_RADIX_PWC_L2_PTE_FROM_L3 ] = { /* 485 */
+	.pme_name = "PM_RADIX_PWC_L2_PTE_FROM_L3",
+	.pme_code = 0x000004F058,
+	.pme_short_desc = "A Page Table Entry was reloaded to a level 2 page walk cache from the core's L3 data cache.",
+	.pme_long_desc = "A Page Table Entry was reloaded to a level 2 page walk cache from the core's L3 data cache. This implies that level 3 and level 4 PWC accesses were not necessary for this translation",
+},
+[ POWER9_PME_PM_LSU3_L1_CAM_CANCEL ] = { /* 486 */
+	.pme_name = "PM_LSU3_L1_CAM_CANCEL",
+	.pme_code = 0x000000F894,
+	.pme_short_desc = "ls3 l1 tm cam cancel",
+	.pme_long_desc = "ls3 l1 tm cam cancel",
+},
+[ POWER9_PME_PM_IC_PREF_CANCEL_HIT ] = { /* 487 */
+	.pme_name = "PM_IC_PREF_CANCEL_HIT",
+	.pme_code = 0x0000004890,
+	.pme_short_desc = "Prefetch Canceled due to icache hit",
+	.pme_long_desc = "Prefetch Canceled due to icache hit",
+},
+[ POWER9_PME_PM_CMPLU_STALL_EIEIO ] = { /* 488 */
+	.pme_name = "PM_CMPLU_STALL_EIEIO",
+	.pme_code = 0x000004D01A,
+	.pme_short_desc = "Finish stall because the NTF instruction is an EIEIO waiting for response from L2",
+	.pme_long_desc = "Finish stall because the NTF instruction is an EIEIO waiting for response from L2",
+},
+[ POWER9_PME_PM_CMPLU_STALL_VDP ] = { /* 489 */
+	.pme_name = "PM_CMPLU_STALL_VDP",
+	.pme_code = 0x000004405C,
+	.pme_short_desc = "Finish stall because the NTF instruction was a vector instruction issued to the Double Precision execution pipe and waiting to finish.",
+	.pme_long_desc = "Finish stall because the NTF instruction was a vector instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Not qualified multicycle. Qualified by vector",
+},
+[ POWER9_PME_PM_DERAT_MISS_1G ] = { /* 490 */
+	.pme_name = "PM_DERAT_MISS_1G",
+	.pme_code = 0x000002C05A,
+	.pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 1G.",
+	.pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 1G. Implies radix translation",
+},
+[ POWER9_PME_PM_DATA_PUMP_CPRED ] = { /* 491 */
+	.pme_name = "PM_DATA_PUMP_CPRED",
+	.pme_code = 0x000001C054,
+	.pme_short_desc = "Pump prediction correct.",
+	.pme_long_desc = "Pump prediction correct. Counts across all types of pumps for a demand load",
+},
+[ POWER9_PME_PM_DPTEG_FROM_L2_MEPF ] = { /* 492 */
+	.pme_name = "PM_DPTEG_FROM_L2_MEPF",
+	.pme_code = 0x000002E040,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_BR_MPRED_TAKEN_CR ] = { /* 493 */
+	.pme_name = "PM_BR_MPRED_TAKEN_CR",
+	.pme_code = 0x00000040B8,
+	.pme_short_desc = "Conditional Branch Completed that was Mispredicted due to the BHT Direction Prediction (taken/not taken).",
+	.pme_long_desc = "Conditional Branch Completed that was Mispredicted due to the BHT Direction Prediction (taken/not taken).",
+},
+[ POWER9_PME_PM_MRK_BRU_FIN ] = { /* 494 */
+	.pme_name = "PM_MRK_BRU_FIN",
+	.pme_code = 0x000002013A,
+	.pme_short_desc = "bru marked instr finish",
+	.pme_long_desc = "bru marked instr finish",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_DL4 ] = { /* 495 */
+	.pme_name = "PM_MRK_DPTEG_FROM_DL4",
+	.pme_code = 0x000003F14C,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_SHL_ST_DEP_CREATED ] = { /* 496 */
+	.pme_name = "PM_SHL_ST_DEP_CREATED",
+	.pme_code = 0x000000588C,
+	.pme_short_desc = "Store-Hit-Load Table Read Hit with entry Enabled",
+	.pme_long_desc = "Store-Hit-Load Table Read Hit with entry Enabled",
+},
+[ POWER9_PME_PM_DPTEG_FROM_L3_1_SHR ] = { /* 497 */
+	.pme_name = "PM_DPTEG_FROM_L3_1_SHR",
+	.pme_code = 0x000001E046,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_DATA_FROM_RL4 ] = { /* 498 */
+	.pme_name = "PM_DATA_FROM_RL4",
+	.pme_code = 0x000002C04A,
+	.pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a demand load",
+},
+[ POWER9_PME_PM_XLATE_MISS ] = { /* 499 */
+	.pme_name = "PM_XLATE_MISS",
+	.pme_code = 0x000000F89C,
+	.pme_short_desc = "The LSU requested a line from L2 for translation.",
+	.pme_long_desc = "The LSU requested a line from L2 for translation. It may be satisfied from any source beyond L2. Includes speculative instructions",
+},
+[ POWER9_PME_PM_CMPLU_STALL_SRQ_FULL ] = { /* 500 */
+	.pme_name = "PM_CMPLU_STALL_SRQ_FULL",
+	.pme_code = 0x0000030016,
+	.pme_short_desc = "Finish stall because the NTF instruction was a store that was held in LSAQ because the SRQ was full",
+	.pme_long_desc = "Finish stall because the NTF instruction was a store that was held in LSAQ because the SRQ was full",
+},
+[ POWER9_PME_PM_SN0_BUSY ] = { /* 501 */
+	.pme_name = "PM_SN0_BUSY",
+	.pme_code = 0x0000026090,
+	.pme_short_desc = "SN mach 0 Busy.",
+	.pme_long_desc = "SN mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)",
+},
+[ POWER9_PME_PM_CMPLU_STALL_NESTED_TBEGIN ] = { /* 502 */
+	.pme_name = "PM_CMPLU_STALL_NESTED_TBEGIN",
+	.pme_code = 0x000001E05C,
+	.pme_short_desc = "Completion stall because the ISU is updating the TEXASR to keep track of the nested tbegin.",
+	.pme_long_desc = "Completion stall because the ISU is updating the TEXASR to keep track of the nested tbegin. This is a short delay, and it includes ROT",
+},
+[ POWER9_PME_PM_ST_CMPL ] = { /* 503 */
+	.pme_name = "PM_ST_CMPL",
+	.pme_code = 0x00000200F0,
+	.pme_short_desc = "Store Instructions Completed",
+	.pme_long_desc = "Store Instructions Completed",
+},
+[ POWER9_PME_PM_DPTEG_FROM_DL2L3_SHR ] = { /* 504 */
+	.pme_name = "PM_DPTEG_FROM_DL2L3_SHR",
+	.pme_code = 0x000003E048,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_DECODE_FUSION_CONST_GEN ] = { /* 505 */
+	.pme_name = "PM_DECODE_FUSION_CONST_GEN",
+	.pme_code = 0x00000048B4,
+	.pme_short_desc = "32-bit constant generation",
+	.pme_long_desc = "32-bit constant generation",
+},
+[ POWER9_PME_PM_L2_LOC_GUESS_CORRECT ] = { /* 506 */
+	.pme_name = "PM_L2_LOC_GUESS_CORRECT",
+	.pme_code = 0x0000016088,
+	.pme_short_desc = "L2 guess loc and guess was correct (ie data local)",
+	.pme_long_desc = "L2 guess loc and guess was correct (ie data local)",
+},
+[ POWER9_PME_PM_INST_FROM_L3_1_ECO_SHR ] = { /* 507 */
+	.pme_name = "PM_INST_FROM_L3_1_ECO_SHR",
+	.pme_code = 0x0000034044,
+	.pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_XLATE_HPT_MODE ] = { /* 508 */
+	.pme_name = "PM_XLATE_HPT_MODE",
+	.pme_code = 0x000000F098,
+	.pme_short_desc = "LSU reports every cycle the thread is in HPT translation mode (as opposed to radix mode)",
+	.pme_long_desc = "LSU reports every cycle the thread is in HPT translation mode (as opposed to radix mode)",
+},
+[ POWER9_PME_PM_CMPLU_STALL_LSU_FIN ] = { /* 509 */
+	.pme_name = "PM_CMPLU_STALL_LSU_FIN",
+	.pme_code = 0x000001003A,
+	.pme_short_desc = "Finish stall because the NTF instruction was an LSU op (other than a load or a store) with all its dependencies met and just going through the LSU pipe to finish",
+	.pme_long_desc = "Finish stall because the NTF instruction was an LSU op (other than a load or a store) with all its dependencies met and just going through the LSU pipe to finish",
+},
+[ POWER9_PME_PM_THRESH_EXC_64 ] = { /* 510 */
+	.pme_name = "PM_THRESH_EXC_64",
+	.pme_code = 0x00000301E8,
+	.pme_short_desc = "Threshold counter exceeded a value of 64",
+	.pme_long_desc = "Threshold counter exceeded a value of 64",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_DL4_CYC ] = { /* 511 */
+	.pme_name = "PM_MRK_DATA_FROM_DL4_CYC",
+	.pme_code = 0x000002C12C,
+	.pme_short_desc = "Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load",
+},
+[ POWER9_PME_PM_DARQ_STORE_XMIT ] = { /* 512 */
+	.pme_name = "PM_DARQ_STORE_XMIT",
+	.pme_code = 0x0000030064,
+	.pme_short_desc = "The DARQ attempted to transmit a store into an LSAQ or SRQ entry.",
+	.pme_long_desc = "The DARQ attempted to transmit a store into an LSAQ or SRQ entry. Includes rejects. Not qualified by thread, so it includes counts for the whole core",
+},
+[ POWER9_PME_PM_DATA_TABLEWALK_CYC ] = { /* 513 */
+	.pme_name = "PM_DATA_TABLEWALK_CYC",
+	.pme_code = 0x000003001A,
+	.pme_short_desc = "Tablwalk Cycles (could be 1 or 2 active tablewalks)",
+	.pme_long_desc = "Tablwalk Cycles (could be 1 or 2 active tablewalks)",
+},
+[ POWER9_PME_PM_L2_RC_ST_DONE ] = { /* 514 */
+	.pme_name = "PM_L2_RC_ST_DONE",
+	.pme_code = 0x0000036086,
+	.pme_short_desc = "RC did st to line that was Tx or Sx",
+	.pme_long_desc = "RC did st to line that was Tx or Sx",
+},
+[ POWER9_PME_PM_TMA_REQ_L2 ] = { /* 515 */
+	.pme_name = "PM_TMA_REQ_L2",
+	.pme_code = 0x000000E0A4,
+	.pme_short_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding",
+	.pme_long_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding",
+},
+[ POWER9_PME_PM_INST_FROM_ON_CHIP_CACHE ] = { /* 516 */
+	.pme_name = "PM_INST_FROM_ON_CHIP_CACHE",
+	.pme_code = 0x0000014048,
+	.pme_short_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_SLB_TABLEWALK_CYC ] = { /* 517 */
+	.pme_name = "PM_SLB_TABLEWALK_CYC",
+	.pme_code = 0x000000F09C,
+	.pme_short_desc = "Cycles when a tablewalk is pending on this thread on the SLB table",
+	.pme_long_desc = "Cycles when a tablewalk is pending on this thread on the SLB table",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_RMEM ] = { /* 518 */
+	.pme_name = "PM_MRK_DATA_FROM_RMEM",
+	.pme_code = 0x000001D148,
+	.pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load",
+},
+[ POWER9_PME_PM_L3_PF_MISS_L3 ] = { /* 519 */
+	.pme_name = "PM_L3_PF_MISS_L3",
+	.pme_code = 0x00000160A0,
+	.pme_short_desc = "L3 Prefetch missed in L3",
+	.pme_long_desc = "L3 Prefetch missed in L3",
+},
+[ POWER9_PME_PM_L3_CI_MISS ] = { /* 520 */
+	.pme_name = "PM_L3_CI_MISS",
+	.pme_code = 0x00000268A2,
+	.pme_short_desc = "L3 castins miss (total count",
+	.pme_long_desc = "L3 castins miss (total count",
+},
+[ POWER9_PME_PM_L2_RCLD_DISP_FAIL_ADDR ] = { /* 521 */
+	.pme_name = "PM_L2_RCLD_DISP_FAIL_ADDR",
+	.pme_code = 0x0000016884,
+	.pme_short_desc = "L2 RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ",
+	.pme_long_desc = "L2 RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ",
+},
+[ POWER9_PME_PM_DERAT_MISS_4K ] = { /* 522 */
+	.pme_name = "PM_DERAT_MISS_4K",
+	.pme_code = 0x000001C056,
+	.pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 4K",
+	.pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 4K",
+},
+[ POWER9_PME_PM_ISIDE_MRU_TOUCH ] = { /* 523 */
+	.pme_name = "PM_ISIDE_MRU_TOUCH",
+	.pme_code = 0x0000046880,
+	.pme_short_desc = "Iside L2 MRU touch",
+	.pme_long_desc = "Iside L2 MRU touch",
+},
+[ POWER9_PME_PM_MRK_RUN_CYC ] = { /* 524 */
+	.pme_name = "PM_MRK_RUN_CYC",
+	.pme_code = 0x000001D15E,
+	.pme_short_desc = "Run cycles in which a marked instruction is in the pipeline",
+	.pme_long_desc = "Run cycles in which a marked instruction is in the pipeline",
+},
+[ POWER9_PME_PM_L3_P0_CO_RTY ] = { /* 525 */
+	.pme_name = "PM_L3_P0_CO_RTY",
+	.pme_code = 0x00000460AE,
+	.pme_short_desc = "L3 CO received retry port 2",
+	.pme_long_desc = "L3 CO received retry port 2",
+},
+[ POWER9_PME_PM_BR_MPRED_CMPL ] = { /* 526 */
+	.pme_name = "PM_BR_MPRED_CMPL",
+	.pme_code = 0x00000400F6,
+	.pme_short_desc = "Number of Branch Mispredicts",
+	.pme_long_desc = "Number of Branch Mispredicts",
+},
+[ POWER9_PME_PM_BR_MPRED_TAKEN_TA ] = { /* 527 */
+	.pme_name = "PM_BR_MPRED_TAKEN_TA",
+	.pme_code = 0x00000048B8,
+	.pme_short_desc = "Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack.",
+	.pme_long_desc = "Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event.",
+},
+[ POWER9_PME_PM_DISP_HELD_TBEGIN ] = { /* 528 */
+	.pme_name = "PM_DISP_HELD_TBEGIN",
+	.pme_code = 0x00000028B0,
+	.pme_short_desc = "This outer tbegin transaction cannot be dispatched until the previous tend instruction completes",
+	.pme_long_desc = "This outer tbegin transaction cannot be dispatched until the previous tend instruction completes",
+},
+[ POWER9_PME_PM_DPTEG_FROM_RL2L3_MOD ] = { /* 529 */
+	.pme_name = "PM_DPTEG_FROM_RL2L3_MOD",
+	.pme_code = 0x000002E046,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_FLUSH_DISP_SB ] = { /* 530 */
+	.pme_name = "PM_FLUSH_DISP_SB",
+	.pme_code = 0x0000002088,
+	.pme_short_desc = "Dispatch Flush: Scoreboard",
+	.pme_long_desc = "Dispatch Flush: Scoreboard",
+},
+[ POWER9_PME_PM_L2_CHIP_PUMP ] = { /* 531 */
+	.pme_name = "PM_L2_CHIP_PUMP",
+	.pme_code = 0x0000046088,
+	.pme_short_desc = "RC requests that were local on chip pump attempts",
+	.pme_long_desc = "RC requests that were local on chip pump attempts",
+},
+[ POWER9_PME_PM_L2_DC_INV ] = { /* 532 */
+	.pme_name = "PM_L2_DC_INV",
+	.pme_code = 0x0000026882,
+	.pme_short_desc = "Dcache invalidates from L2",
+	.pme_long_desc = "Dcache invalidates from L2",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC ] = { /* 533 */
+	.pme_name = "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC",
+	.pme_code = 0x000001415A,
+	.pme_short_desc = "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_L3_1_SHR ] = { /* 534 */
+	.pme_name = "PM_MRK_DPTEG_FROM_L3_1_SHR",
+	.pme_code = 0x000001F146,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a marked data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_MRK_DERAT_MISS_2M ] = { /* 535 */
+	.pme_name = "PM_MRK_DERAT_MISS_2M",
+	.pme_code = 0x000002D152,
+	.pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 2M.",
+	.pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 2M. Implies radix translation",
+},
+[ POWER9_PME_PM_MRK_ST_DONE_L2 ] = { /* 536 */
+	.pme_name = "PM_MRK_ST_DONE_L2",
+	.pme_code = 0x0000010134,
+	.pme_short_desc = "marked store completed in L2 ( RC machine done)",
+	.pme_long_desc = "marked store completed in L2 ( RC machine done)",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L3_1_ECO_MOD ] = { /* 537 */
+	.pme_name = "PM_MRK_DATA_FROM_L3_1_ECO_MOD",
+	.pme_code = 0x000004D144,
+	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked load",
+},
+[ POWER9_PME_PM_IPTEG_FROM_RMEM ] = { /* 538 */
+	.pme_name = "PM_IPTEG_FROM_RMEM",
+	.pme_code = 0x000003504A,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request",
+},
+[ POWER9_PME_PM_MRK_LSU_FLUSH_EMSH ] = { /* 539 */
+	.pme_name = "PM_MRK_LSU_FLUSH_EMSH",
+	.pme_code = 0x000000D898,
+	.pme_short_desc = "An ERAT miss was detected after a set-p hit.",
+	.pme_long_desc = "An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due to tlbmiss and the instruction gets flushed because the instruction was working on the wrong address",
+},
+[ POWER9_PME_PM_BR_PRED_LSTACK ] = { /* 540 */
+	.pme_name = "PM_BR_PRED_LSTACK",
+	.pme_code = 0x00000040A8,
+	.pme_short_desc = "Conditional Branch Completed that used the Link Stack for Target Prediction",
+	.pme_long_desc = "Conditional Branch Completed that used the Link Stack for Target Prediction",
+},
+[ POWER9_PME_PM_L3_P0_CO_MEM ] = { /* 541 */
+	.pme_name = "PM_L3_P0_CO_MEM",
+	.pme_code = 0x00000360AA,
+	.pme_short_desc = "l3 CO to memory port 0",
+	.pme_long_desc = "l3 CO to memory port 0",
+},
+[ POWER9_PME_PM_IPTEG_FROM_L2_MEPF ] = { /* 542 */
+	.pme_name = "PM_IPTEG_FROM_L2_MEPF",
+	.pme_code = 0x0000025040,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request",
+},
+[ POWER9_PME_PM_LS0_ERAT_MISS_PREF ] = { /* 543 */
+	.pme_name = "PM_LS0_ERAT_MISS_PREF",
+	.pme_code = 0x000000E084,
+	.pme_short_desc = "LS0 Erat miss due to prefetch",
+	.pme_long_desc = "LS0 Erat miss due to prefetch",
+},
+[ POWER9_PME_PM_RD_HIT_PF ] = { /* 544 */
+	.pme_name = "PM_RD_HIT_PF",
+	.pme_code = 0x00000268A8,
+	.pme_short_desc = "rd machine hit l3 pf machine",
+	.pme_long_desc = "rd machine hit l3 pf machine",
+},
+[ POWER9_PME_PM_DECODE_FUSION_LD_ST_DISP ] = { /* 545 */
+	.pme_name = "PM_DECODE_FUSION_LD_ST_DISP",
+	.pme_code = 0x00000048A8,
+	.pme_short_desc = "32-bit displacement D-form and 16-bit displacement X-form",
+	.pme_long_desc = "32-bit displacement D-form and 16-bit displacement X-form",
+},
+[ POWER9_PME_PM_CMPLU_STALL_NTC_DISP_FIN ] = { /* 546 */
+	.pme_name = "PM_CMPLU_STALL_NTC_DISP_FIN",
+	.pme_code = 0x000004E018,
+	.pme_short_desc = "Finish stall because the NTF instruction was one that must finish at dispatch.",
+	.pme_long_desc = "Finish stall because the NTF instruction was one that must finish at dispatch.",
+},
+[ POWER9_PME_PM_ICT_NOSLOT_CYC ] = { /* 547 */
+	.pme_name = "PM_ICT_NOSLOT_CYC",
+	.pme_code = 0x00000100F8,
+	.pme_short_desc = "Number of cycles the ICT has no itags assigned to this thread",
+	.pme_long_desc = "Number of cycles the ICT has no itags assigned to this thread",
+},
+[ POWER9_PME_PM_DERAT_MISS_16M ] = { /* 548 */
+	.pme_name = "PM_DERAT_MISS_16M",
+	.pme_code = 0x000003C054,
+	.pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 16M",
+	.pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 16M",
+},
+[ POWER9_PME_PM_IC_MISS_ICBI ] = { /* 549 */
+	.pme_name = "PM_IC_MISS_ICBI",
+	.pme_code = 0x0000005094,
+	.pme_short_desc = "threaded version, IC Misses where we got EA dir hit but no sector valids were on.",
+	.pme_long_desc = "threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out",
+},
+[ POWER9_PME_PM_TAGE_OVERRIDE_WRONG_SPEC ] = { /* 550 */
+	.pme_name = "PM_TAGE_OVERRIDE_WRONG_SPEC",
+	.pme_code = 0x00000058B8,
+	.pme_short_desc = "The TAGE overrode BHT direction prediction and it was correct.",
+	.pme_long_desc = "The TAGE overrode BHT direction prediction and it was correct. Includes taken and not taken and is counted at execution time",
+},
+[ POWER9_PME_PM_ICT_NOSLOT_DISP_HELD_TBEGIN ] = { /* 551 */
+	.pme_name = "PM_ICT_NOSLOT_DISP_HELD_TBEGIN",
+	.pme_code = 0x0000010064,
+	.pme_short_desc = "the NTC instruction is being held at dispatch because it is a tbegin instruction and there is an older tbegin in the pipeline that must complete before the younger tbegin can dispatch",
+	.pme_long_desc = "the NTC instruction is being held at dispatch because it is a tbegin instruction and there is an older tbegin in the pipeline that must complete before the younger tbegin can dispatch",
+},
+[ POWER9_PME_PM_MRK_BR_TAKEN_CMPL ] = { /* 552 */
+	.pme_name = "PM_MRK_BR_TAKEN_CMPL",
+	.pme_code = 0x00000101E2,
+	.pme_short_desc = "Marked Branch Taken completed",
+	.pme_long_desc = "Marked Branch Taken completed",
+},
+[ POWER9_PME_PM_CMPLU_STALL_VFXU ] = { /* 553 */
+	.pme_name = "PM_CMPLU_STALL_VFXU",
+	.pme_code = 0x000003C05C,
+	.pme_short_desc = "Finish stall due to a vector fixed point instruction in the execution pipeline.",
+	.pme_long_desc = "Finish stall due to a vector fixed point instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes",
+},
+[ POWER9_PME_PM_DATA_GRP_PUMP_MPRED_RTY ] = { /* 554 */
+	.pme_name = "PM_DATA_GRP_PUMP_MPRED_RTY",
+	.pme_code = 0x000001C052,
+	.pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load",
+	.pme_long_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load",
+},
+[ POWER9_PME_PM_INST_FROM_L3 ] = { /* 555 */
+	.pme_name = "PM_INST_FROM_L3",
+	.pme_code = 0x0000044042,
+	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_ITLB_MISS ] = { /* 556 */
+	.pme_name = "PM_ITLB_MISS",
+	.pme_code = 0x00000400FC,
+	.pme_short_desc = "ITLB Reloaded (always zero on POWER6)",
+	.pme_long_desc = "ITLB Reloaded (always zero on POWER6)",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_RL2L3_MOD ] = { /* 557 */
+	.pme_name = "PM_MRK_DPTEG_FROM_RL2L3_MOD",
+	.pme_code = 0x000002F146,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_LSU2_TM_L1_MISS ] = { /* 558 */
+	.pme_name = "PM_LSU2_TM_L1_MISS",
+	.pme_code = 0x000000E0A0,
+	.pme_short_desc = "Load tm L1 miss",
+	.pme_long_desc = "Load tm L1 miss",
+},
+[ POWER9_PME_PM_L3_WI_USAGE ] = { /* 559 */
+	.pme_name = "PM_L3_WI_USAGE",
+	.pme_code = 0x00000168A8,
+	.pme_short_desc = "rotating sample of 8 WI actives",
+	.pme_long_desc = "rotating sample of 8 WI actives",
+},
+[ POWER9_PME_PM_L2_SN_M_WR_DONE ] = { /* 560 */
+	.pme_name = "PM_L2_SN_M_WR_DONE",
+	.pme_code = 0x0000046886,
+	.pme_short_desc = "SNP dispatched for a write and was M",
+	.pme_long_desc = "SNP dispatched for a write and was M",
+},
+[ POWER9_PME_PM_DISP_HELD_SYNC_HOLD ] = { /* 561 */
+	.pme_name = "PM_DISP_HELD_SYNC_HOLD",
+	.pme_code = 0x000004003C,
+	.pme_short_desc = "Cycles in which dispatch is held because of a synchronizing instruction in the pipeline",
+	.pme_long_desc = "Cycles in which dispatch is held because of a synchronizing instruction in the pipeline",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_L2_1_SHR ] = { /* 562 */
+	.pme_name = "PM_MRK_DPTEG_FROM_L2_1_SHR",
+	.pme_code = 0x000003F146,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a marked data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_MEM_PREF ] = { /* 563 */
+	.pme_name = "PM_MEM_PREF",
+	.pme_code = 0x000002C058,
+	.pme_short_desc = "Memory prefetch for this thread.",
+	.pme_long_desc = "Memory prefetch for this thread. Includes L4",
+},
+[ POWER9_PME_PM_L2_SN_M_RD_DONE ] = { /* 564 */
+	.pme_name = "PM_L2_SN_M_RD_DONE",
+	.pme_code = 0x0000046086,
+	.pme_short_desc = "SNP dispatched for a read and was M",
+	.pme_long_desc = "SNP dispatched for a read and was M",
+},
+[ POWER9_PME_PM_LS0_UNALIGNED_ST ] = { /* 565 */
+	.pme_name = "PM_LS0_UNALIGNED_ST",
+	.pme_code = 0x000000F0B8,
+	.pme_short_desc = "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size.",
+	.pme_long_desc = "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty",
+},
+[ POWER9_PME_PM_DC_PREF_CONS_ALLOC ] = { /* 566 */
+	.pme_name = "PM_DC_PREF_CONS_ALLOC",
+	.pme_code = 0x000000F0B4,
+	.pme_short_desc = "Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch",
+	.pme_long_desc = "Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch",
+},
+[ POWER9_PME_PM_MRK_DERAT_MISS_16G ] = { /* 567 */
+	.pme_name = "PM_MRK_DERAT_MISS_16G",
+	.pme_code = 0x000004C15C,
+	.pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 16G",
+	.pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 16G",
+},
+[ POWER9_PME_PM_IPTEG_FROM_L2 ] = { /* 568 */
+	.pme_name = "PM_IPTEG_FROM_L2",
+	.pme_code = 0x0000015042,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request",
+},
+[ POWER9_PME_PM_ANY_THRD_RUN_CYC ] = { /* 569 */
+	.pme_name = "PM_ANY_THRD_RUN_CYC",
+	.pme_code = 0x00000100FA,
+	.pme_short_desc = "Cycles in which at least one thread has the run latch set",
+	.pme_long_desc = "Cycles in which at least one thread has the run latch set",
+},
+[ POWER9_PME_PM_MRK_PROBE_NOP_CMPL ] = { /* 570 */
+	.pme_name = "PM_MRK_PROBE_NOP_CMPL",
+	.pme_code = 0x000001F05E,
+	.pme_short_desc = "Marked probeNops completed",
+	.pme_long_desc = "Marked probeNops completed",
+},
+[ POWER9_PME_PM_BANK_CONFLICT ] = { /* 571 */
+	.pme_name = "PM_BANK_CONFLICT",
+	.pme_code = 0x0000004880,
+	.pme_short_desc = "Read blocked due to interleave conflict.",
+	.pme_long_desc = "Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle.",
+},
+[ POWER9_PME_PM_INST_SYS_PUMP_MPRED ] = { /* 572 */
+	.pme_name = "PM_INST_SYS_PUMP_MPRED",
+	.pme_code = 0x0000034052,
+	.pme_short_desc = "Final Pump Scope (system) mispredicted.",
+	.pme_long_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for an instruction fetch",
+},
+[ POWER9_PME_PM_NON_DATA_STORE ] = { /* 573 */
+	.pme_name = "PM_NON_DATA_STORE",
+	.pme_code = 0x000000F8A0,
+	.pme_short_desc = "All ops that drain from s2q to L2 and contain no data",
+	.pme_long_desc = "All ops that drain from s2q to L2 and contain no data",
+},
+[ POWER9_PME_PM_DC_PREF_CONF ] = { /* 574 */
+	.pme_name = "PM_DC_PREF_CONF",
+	.pme_code = 0x000000F0A8,
+	.pme_short_desc = "A demand load referenced a line in an active prefetch stream.",
+	.pme_long_desc = "A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Includes forwards and backwards streams",
+},
+[ POWER9_PME_PM_BTAC_BAD_RESULT ] = { /* 575 */
+	.pme_name = "PM_BTAC_BAD_RESULT",
+	.pme_code = 0x00000050B0,
+	.pme_short_desc = "BTAC thinks branch will be taken but it is either predicted not-taken by the BHT, or the target address is wrong (less common).",
+	.pme_long_desc = "BTAC thinks branch will be taken but it is either predicted not-taken by the BHT, or the target address is wrong (less common). In both cases, a redirect will happen",
+},
+[ POWER9_PME_PM_LSU_LMQ_FULL_CYC ] = { /* 576 */
+	.pme_name = "PM_LSU_LMQ_FULL_CYC",
+	.pme_code = 0x000000D0B8,
+	.pme_short_desc = "Counts the number of cycles the LMQ is full",
+	.pme_long_desc = "Counts the number of cycles the LMQ is full",
+},
+[ POWER9_PME_PM_NON_MATH_FLOP_CMPL ] = { /* 577 */
+	.pme_name = "PM_NON_MATH_FLOP_CMPL",
+	.pme_code = 0x000004D05A,
+	.pme_short_desc = "Non-math flop instruction completed",
+	.pme_long_desc = "Non-math flop instruction completed",
+},
+[ POWER9_PME_PM_MRK_LD_MISS_L1_CYC ] = { /* 578 */
+	.pme_name = "PM_MRK_LD_MISS_L1_CYC",
+	.pme_code = 0x000001D056,
+	.pme_short_desc = "Marked ld latency",
+	.pme_long_desc = "Marked ld latency",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L2_CYC ] = { /* 579 */
+	.pme_name = "PM_MRK_DATA_FROM_L2_CYC",
+	.pme_code = 0x0000014156,
+	.pme_short_desc = "Duration in cycles to reload from local core's L2 due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload from local core's L2 due to a marked load",
+},
+[ POWER9_PME_PM_FXU_1PLUS_BUSY ] = { /* 580 */
+	.pme_name = "PM_FXU_1PLUS_BUSY",
+	.pme_code = 0x000003000E,
+	.pme_short_desc = "At least one of the 4 FXU units is busy",
+	.pme_long_desc = "At least one of the 4 FXU units is busy",
+},
+[ POWER9_PME_PM_CMPLU_STALL_DP ] = { /* 581 */
+	.pme_name = "PM_CMPLU_STALL_DP",
+	.pme_code = 0x000001005C,
+	.pme_short_desc = "Finish stall because the NTF instruction was a scalar instruction issued to the Double Precision execution pipe and waiting to finish.",
+	.pme_long_desc = "Finish stall because the NTF instruction was a scalar instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Not qualified multicycle. Qualified by NOT vector",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L3_1_MOD_CYC ] = { /* 582 */
+	.pme_name = "PM_MRK_DATA_FROM_L3_1_MOD_CYC",
+	.pme_code = 0x000001D140,
+	.pme_short_desc = "Duration in cycles to reload with Modified (M) data from another core's L3 on the same chip due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload with Modified (M) data from another core's L3 on the same chip due to a marked load",
+},
+[ POWER9_PME_PM_SYNC_MRK_L2HIT ] = { /* 583 */
+	.pme_name = "PM_SYNC_MRK_L2HIT",
+	.pme_code = 0x0000015158,
+	.pme_short_desc = "Marked L2 Hits that can throw a synchronous interrupt",
+	.pme_long_desc = "Marked L2 Hits that can throw a synchronous interrupt",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_RMEM_CYC ] = { /* 584 */
+	.pme_name = "PM_MRK_DATA_FROM_RMEM_CYC",
+	.pme_code = 0x000002C12A,
+	.pme_short_desc = "Duration in cycles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load",
+},
+[ POWER9_PME_PM_ISU1_ISS_HOLD_ALL ] = { /* 585 */
+	.pme_name = "PM_ISU1_ISS_HOLD_ALL",
+	.pme_code = 0x0000003084,
+	.pme_short_desc = "All ISU rejects",
+	.pme_long_desc = "All ISU rejects",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT ] = { /* 586 */
+	.pme_name = "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT",
+	.pme_code = 0x000003F142,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_MRK_FAB_RSP_RWITM_RTY ] = { /* 587 */
+	.pme_name = "PM_MRK_FAB_RSP_RWITM_RTY",
+	.pme_code = 0x000002015E,
+	.pme_short_desc = "Sampled store did a rwitm and got a rty",
+	.pme_long_desc = "Sampled store did a rwitm and got a rty",
+},
+[ POWER9_PME_PM_L3_P3_LCO_RTY ] = { /* 588 */
+	.pme_name = "PM_L3_P3_LCO_RTY",
+	.pme_code = 0x00000268B4,
+	.pme_short_desc = "L3 lateral cast out received retry on port 3",
+	.pme_long_desc = "L3 lateral cast out received retry on port 3",
+},
+[ POWER9_PME_PM_PUMP_CPRED ] = { /* 589 */
+	.pme_name = "PM_PUMP_CPRED",
+	.pme_code = 0x0000010054,
+	.pme_short_desc = "Pump prediction correct.",
+	.pme_long_desc = "Pump prediction correct. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
+},
+[ POWER9_PME_PM_LS3_TM_DISALLOW ] = { /* 590 */
+	.pme_name = "PM_LS3_TM_DISALLOW",
+	.pme_code = 0x000000E8B8,
+	.pme_short_desc = "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it",
+	.pme_long_desc = "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it",
+},
+[ POWER9_PME_PM_SN_INVL ] = { /* 591 */
+	.pme_name = "PM_SN_INVL",
+	.pme_code = 0x00000368A8,
+	.pme_short_desc = "Any port snooper detects a store to a line that?s in the Sx state and invalidates the line.",
+	.pme_long_desc = "Any port snooper detects a store to a line that?s in the Sx state and invalidates the line. Up to 4 can happen in a cycle but we only count 1",
+},
+[ POWER9_PME_PM_TM_LD_CONF ] = { /* 592 */
+	.pme_name = "PM_TM_LD_CONF",
+	.pme_code = 0x000002608C,
+	.pme_short_desc = "TM Load (fav or non-fav) ran into conflict (failed)",
+	.pme_long_desc = "TM Load (fav or non-fav) ran into conflict (failed)",
+},
+[ POWER9_PME_PM_LD_MISS_L1_FIN ] = { /* 593 */
+	.pme_name = "PM_LD_MISS_L1_FIN",
+	.pme_code = 0x000002C04E,
+	.pme_short_desc = "Number of load instructions that finished with an L1 miss.",
+	.pme_long_desc = "Number of load instructions that finished with an L1 miss. Note that even if a load spans multiple slices this event will increment only once per load op.",
+},
+[ POWER9_PME_PM_SYNC_MRK_PROBE_NOP ] = { /* 594 */
+	.pme_name = "PM_SYNC_MRK_PROBE_NOP",
+	.pme_code = 0x0000015150,
+	.pme_short_desc = "Marked probeNops which can cause synchronous interrupts",
+	.pme_long_desc = "Marked probeNops which can cause synchronous interrupts",
+},
+[ POWER9_PME_PM_RUN_CYC ] = { /* 595 */
+	.pme_name = "PM_RUN_CYC",
+	.pme_code = 0x00000200F4,
+	.pme_short_desc = "Run_cycles",
+	.pme_long_desc = "Run_cycles",
+},
+[ POWER9_PME_PM_SYS_PUMP_MPRED ] = { /* 596 */
+	.pme_name = "PM_SYS_PUMP_MPRED",
+	.pme_code = 0x0000030052,
+	.pme_short_desc = "Final Pump Scope (system) mispredicted.",
+	.pme_long_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
+},
+[ POWER9_PME_PM_DATA_FROM_OFF_CHIP_CACHE ] = { /* 597 */
+	.pme_name = "PM_DATA_FROM_OFF_CHIP_CACHE",
+	.pme_code = 0x000004C04A,
+	.pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a demand load",
+},
+[ POWER9_PME_PM_TM_NESTED_TBEGIN ] = { /* 598 */
+	.pme_name = "PM_TM_NESTED_TBEGIN",
+	.pme_code = 0x00000020A0,
+	.pme_short_desc = "Completion Tm nested tbegin",
+	.pme_long_desc = "Completion Tm nested tbegin",
+},
+[ POWER9_PME_PM_FLUSH_COMPLETION ] = { /* 599 */
+	.pme_name = "PM_FLUSH_COMPLETION",
+	.pme_code = 0x0000030012,
+	.pme_short_desc = "The instruction that was next to complete did not complete because it suffered a flush",
+	.pme_long_desc = "The instruction that was next to complete did not complete because it suffered a flush",
+},
+[ POWER9_PME_PM_ST_MISS_L1 ] = { /* 600 */
+	.pme_name = "PM_ST_MISS_L1",
+	.pme_code = 0x00000300F0,
+	.pme_short_desc = "Store Missed L1",
+	.pme_long_desc = "Store Missed L1",
+},
+[ POWER9_PME_PM_IPTEG_FROM_L2MISS ] = { /* 601 */
+	.pme_name = "PM_IPTEG_FROM_L2MISS",
+	.pme_code = 0x000001504E,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a instruction side request",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a instruction side request",
+},
+[ POWER9_PME_PM_LSU3_TM_L1_MISS ] = { /* 602 */
+	.pme_name = "PM_LSU3_TM_L1_MISS",
+	.pme_code = 0x000000E8A0,
+	.pme_short_desc = "Load tm L1 miss",
+	.pme_long_desc = "Load tm L1 miss",
+},
+[ POWER9_PME_PM_L3_CO ] = { /* 603 */
+	.pme_name = "PM_L3_CO",
+	.pme_code = 0x00000360A8,
+	.pme_short_desc = "l3 castout occuring ( does not include casthrough or log writes (cinj/dmaw)",
+	.pme_long_desc = "l3 castout occuring ( does not include casthrough or log writes (cinj/dmaw)",
+},
+[ POWER9_PME_PM_MRK_STALL_CMPLU_CYC ] = { /* 604 */
+	.pme_name = "PM_MRK_STALL_CMPLU_CYC",
+	.pme_code = 0x000003013E,
+	.pme_short_desc = "Number of cycles the marked instruction is experiencing a stall while it is next to complete (NTC)",
+	.pme_long_desc = "Number of cycles the marked instruction is experiencing a stall while it is next to complete (NTC)",
+},
+[ POWER9_PME_PM_INST_FROM_DL2L3_SHR ] = { /* 605 */
+	.pme_name = "PM_INST_FROM_DL2L3_SHR",
+	.pme_code = 0x0000034048,
+	.pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_SCALAR_FLOP_CMPL ] = { /* 606 */
+	.pme_name = "PM_SCALAR_FLOP_CMPL",
+	.pme_code = 0x0000010130,
+	.pme_short_desc = "Scalar flop events",
+	.pme_long_desc = "Scalar flop events",
+},
+[ POWER9_PME_PM_LRQ_REJECT ] = { /* 607 */
+	.pme_name = "PM_LRQ_REJECT",
+	.pme_code = 0x000002E05A,
+	.pme_short_desc = "Internal LSU reject from LRQ.",
+	.pme_long_desc = "Internal LSU reject from LRQ. Rejects cause the load to go back to LRQ, but it stays contained within the LSU once it gets issued. This event counts the number of times the LRQ attempts to relaunch an instruction after a reject. Any load can suffer multiple rejects",
+},
+[ POWER9_PME_PM_4FLOP_CMPL ] = { /* 608 */
+	.pme_name = "PM_4FLOP_CMPL",
+	.pme_code = 0x000001000E,
+	.pme_short_desc = "four flop events",
+	.pme_long_desc = "four flop events",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_RMEM ] = { /* 609 */
+	.pme_name = "PM_MRK_DPTEG_FROM_RMEM",
+	.pme_code = 0x000003F14A,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_LD_CMPL ] = { /* 610 */
+	.pme_name = "PM_LD_CMPL",
+	.pme_code = 0x000004003E,
+	.pme_short_desc = "count of Loads completed",
+	.pme_long_desc = "count of Loads completed",
+},
+[ POWER9_PME_PM_DATA_FROM_L3_MEPF ] = { /* 611 */
+	.pme_name = "PM_DATA_FROM_L3_MEPF",
+	.pme_code = 0x000002C042,
+	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load",
+},
+[ POWER9_PME_PM_L1PF_L2MEMACC ] = { /* 612 */
+	.pme_name = "PM_L1PF_L2MEMACC",
+	.pme_code = 0x0000016890,
+	.pme_short_desc = "valid when first beat of data comes in for an L1pref where data came from mem(or L4)",
+	.pme_long_desc = "valid when first beat of data comes in for an L1pref where data came from mem(or L4)",
+},
+[ POWER9_PME_PM_INST_FROM_L3MISS ] = { /* 613 */
+	.pme_name = "PM_INST_FROM_L3MISS",
+	.pme_code = 0x00000300FA,
+	.pme_short_desc = "Marked instruction was reloaded from a location beyond the local chiplet",
+	.pme_long_desc = "Marked instruction was reloaded from a location beyond the local chiplet",
+},
+[ POWER9_PME_PM_MRK_LSU_FLUSH_LHS ] = { /* 614 */
+	.pme_name = "PM_MRK_LSU_FLUSH_LHS",
+	.pme_code = 0x000000D0A0,
+	.pme_short_desc = "Effective Address alias flush : no EA match but Real Address match.",
+	.pme_long_desc = "Effective Address alias flush : no EA match but Real Address match. If the data has not yet been returned for this load, the instruction will just be rejected, but if it has returned data, it will be flushed",
+},
+[ POWER9_PME_PM_EE_OFF_EXT_INT ] = { /* 615 */
+	.pme_name = "PM_EE_OFF_EXT_INT",
+	.pme_code = 0x0000002080,
+	.pme_short_desc = "CyclesMSR[EE] is off and external interrupts are active",
+	.pme_long_desc = "CyclesMSR[EE] is off and external interrupts are active",
+},
+[ POWER9_PME_PM_TM_ST_CONF ] = { /* 616 */
+	.pme_name = "PM_TM_ST_CONF",
+	.pme_code = 0x000003608C,
+	.pme_short_desc = "TM Store (fav or non-fav) ran into conflict (failed)",
+	.pme_long_desc = "TM Store (fav or non-fav) ran into conflict (failed)",
+},
+[ POWER9_PME_PM_PMC6_OVERFLOW ] = { /* 617 */
+	.pme_name = "PM_PMC6_OVERFLOW",
+	.pme_code = 0x0000030024,
+	.pme_short_desc = "Overflow from counter 6",
+	.pme_long_desc = "Overflow from counter 6",
+},
+[ POWER9_PME_PM_INST_FROM_DL2L3_MOD ] = { /* 618 */
+	.pme_name = "PM_INST_FROM_DL2L3_MOD",
+	.pme_code = 0x0000044048,
+	.pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_MRK_INST_CMPL ] = { /* 619 */
+	.pme_name = "PM_MRK_INST_CMPL",
+	.pme_code = 0x00000401E0,
+	.pme_short_desc = "marked instruction completed",
+	.pme_long_desc = "marked instruction completed",
+},
+[ POWER9_PME_PM_TAGE_CORRECT_TAKEN_CMPL ] = { /* 620 */
+	.pme_name = "PM_TAGE_CORRECT_TAKEN_CMPL",
+	.pme_code = 0x00000050B4,
+	.pme_short_desc = "The TAGE overrode BHT direction prediction and it was correct.",
+	.pme_long_desc = "The TAGE overrode BHT direction prediction and it was correct. Counted at completion for taken branches only",
+},
+[ POWER9_PME_PM_MRK_L1_ICACHE_MISS ] = { /* 621 */
+	.pme_name = "PM_MRK_L1_ICACHE_MISS",
+	.pme_code = 0x00000101E4,
+	.pme_short_desc = "sampled Instruction suffered an icache Miss",
+	.pme_long_desc = "sampled Instruction suffered an icache Miss",
+},
+[ POWER9_PME_PM_TLB_MISS ] = { /* 622 */
+	.pme_name = "PM_TLB_MISS",
+	.pme_code = 0x0000020066,
+	.pme_short_desc = "TLB Miss (I + D)",
+	.pme_long_desc = "TLB Miss (I + D)",
+},
+[ POWER9_PME_PM_L2_RCLD_DISP_FAIL_OTHER ] = { /* 623 */
+	.pme_name = "PM_L2_RCLD_DISP_FAIL_OTHER",
+	.pme_code = 0x0000026084,
+	.pme_short_desc = "L2 RC load dispatch attempt failed due to other reasons",
+	.pme_long_desc = "L2 RC load dispatch attempt failed due to other reasons",
+},
+[ POWER9_PME_PM_FXU_BUSY ] = { /* 624 */
+	.pme_name = "PM_FXU_BUSY",
+	.pme_code = 0x000002000A,
+	.pme_short_desc = "Cycles in which all 4 FXUs are busy.",
+	.pme_long_desc = "Cycles in which all 4 FXUs are busy. The FXU is running at capacity",
+},
+[ POWER9_PME_PM_DATA_FROM_L3_DISP_CONFLICT ] = { /* 625 */
+	.pme_name = "PM_DATA_FROM_L3_DISP_CONFLICT",
+	.pme_code = 0x000003C042,
+	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a demand load",
+},
+[ POWER9_PME_PM_INST_FROM_L3_1_MOD ] = { /* 626 */
+	.pme_name = "PM_INST_FROM_L3_1_MOD",
+	.pme_code = 0x0000024044,
+	.pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_LSU_REJECT_LMQ_FULL ] = { /* 627 */
+	.pme_name = "PM_LSU_REJECT_LMQ_FULL",
+	.pme_code = 0x000003001C,
+	.pme_short_desc = "LSU Reject due to LMQ full (up to 4 per cycles)",
+	.pme_long_desc = "LSU Reject due to LMQ full (up to 4 per cycles)",
+},
+[ POWER9_PME_PM_CO_DISP_FAIL ] = { /* 628 */
+	.pme_name = "PM_CO_DISP_FAIL",
+	.pme_code = 0x0000016886,
+	.pme_short_desc = "CO dispatch failed due to all CO machines being busy",
+	.pme_long_desc = "CO dispatch failed due to all CO machines being busy",
+},
+[ POWER9_PME_PM_L3_TRANS_PF ] = { /* 629 */
+	.pme_name = "PM_L3_TRANS_PF",
+	.pme_code = 0x00000468A4,
+	.pme_short_desc = "L3 Transient prefetch",
+	.pme_long_desc = "L3 Transient prefetch",
+},
+[ POWER9_PME_PM_MRK_ST_NEST ] = { /* 630 */
+	.pme_name = "PM_MRK_ST_NEST",
+	.pme_code = 0x0000020138,
+	.pme_short_desc = "Marked store sent to nest",
+	.pme_long_desc = "Marked store sent to nest",
+},
+[ POWER9_PME_PM_LSU1_L1_CAM_CANCEL ] = { /* 631 */
+	.pme_name = "PM_LSU1_L1_CAM_CANCEL",
+	.pme_code = 0x000000F890,
+	.pme_short_desc = "ls1 l1 tm cam cancel",
+	.pme_long_desc = "ls1 l1 tm cam cancel",
+},
+[ POWER9_PME_PM_INST_CHIP_PUMP_CPRED ] = { /* 632 */
+	.pme_name = "PM_INST_CHIP_PUMP_CPRED",
+	.pme_code = 0x0000014050,
+	.pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch",
+	.pme_long_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch",
+},
+[ POWER9_PME_PM_LSU3_VECTOR_ST_FIN ] = { /* 633 */
+	.pme_name = "PM_LSU3_VECTOR_ST_FIN",
+	.pme_code = 0x000000C88C,
+	.pme_short_desc = "A vector store instruction finished.",
+	.pme_long_desc = "A vector store instruction finished. The ops considered in this category are stv*, stxv*, stxsi*x, stxsd, and stxssp",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_L2_1_MOD ] = { /* 634 */
+	.pme_name = "PM_MRK_DPTEG_FROM_L2_1_MOD",
+	.pme_code = 0x000004F146,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a marked data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_IBUF_FULL_CYC ] = { /* 635 */
+	.pme_name = "PM_IBUF_FULL_CYC",
+	.pme_code = 0x0000004884,
+	.pme_short_desc = "Cycles No room in ibuff",
+	.pme_long_desc = "Cycles No room in ibuff",
+},
+[ POWER9_PME_PM_8FLOP_CMPL ] = { /* 636 */
+	.pme_name = "PM_8FLOP_CMPL",
+	.pme_code = 0x000004D054,
+	.pme_short_desc = "",
+	.pme_long_desc = "",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_DL2L3_SHR_CYC ] = { /* 637 */
+	.pme_name = "PM_MRK_DATA_FROM_DL2L3_SHR_CYC",
+	.pme_code = 0x000002C128,
+	.pme_short_desc = "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE ] = { /* 638 */
+	.pme_name = "PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE",
+	.pme_code = 0x000004F14A,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_ICT_NOSLOT_IC_L3 ] = { /* 639 */
+	.pme_name = "PM_ICT_NOSLOT_IC_L3",
+	.pme_code = 0x000003E052,
+	.pme_short_desc = "Ict empty for this thread due to icache misses that were sourced from the local L3",
+	.pme_long_desc = "Ict empty for this thread due to icache misses that were sourced from the local L3",
+},
+[ POWER9_PME_PM_CMPLU_STALL_LWSYNC ] = { /* 640 */
+	.pme_name = "PM_CMPLU_STALL_LWSYNC",
+	.pme_code = 0x0000010036,
+	.pme_short_desc = "completion stall due to lwsync",
+	.pme_long_desc = "completion stall due to lwsync",
+},
+[ POWER9_PME_PM_RADIX_PWC_L2_PDE_FROM_L2 ] = { /* 641 */
+	.pme_name = "PM_RADIX_PWC_L2_PDE_FROM_L2",
+	.pme_code = 0x000002D028,
+	.pme_short_desc = "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache",
+	.pme_long_desc = "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_RL2L3_SHR_CYC ] = { /* 642 */
+	.pme_name = "PM_MRK_DATA_FROM_RL2L3_SHR_CYC",
+	.pme_code = 0x000004C12A,
+	.pme_short_desc = "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
+},
+[ POWER9_PME_PM_L3_SN0_BUSY ] = { /* 643 */
+	.pme_name = "PM_L3_SN0_BUSY",
+	.pme_code = 0x00000460AC,
+	.pme_short_desc = "lifetime, sample of snooper machine 0 valid",
+	.pme_long_desc = "lifetime, sample of snooper machine 0 valid",
+},
+[ POWER9_PME_PM_TM_OUTER_TBEGIN_DISP ] = { /* 644 */
+	.pme_name = "PM_TM_OUTER_TBEGIN_DISP",
+	.pme_code = 0x000004E05E,
+	.pme_short_desc = "Number of outer tbegin instructions dispatched.",
+	.pme_long_desc = "Number of outer tbegin instructions dispatched. The dispatch unit determines whether the tbegin instruction is outer or nested. This is a speculative count, which includes flushed instructions",
+},
+[ POWER9_PME_PM_GRP_PUMP_MPRED ] = { /* 645 */
+	.pme_name = "PM_GRP_PUMP_MPRED",
+	.pme_code = 0x0000020052,
+	.pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
+	.pme_long_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
+},
+[ POWER9_PME_PM_SRQ_EMPTY_CYC ] = { /* 646 */
+	.pme_name = "PM_SRQ_EMPTY_CYC",
+	.pme_code = 0x0000040008,
+	.pme_short_desc = "Cycles in which the SRQ has at least one (out of four) empty slice",
+	.pme_long_desc = "Cycles in which the SRQ has at least one (out of four) empty slice",
+},
+[ POWER9_PME_PM_LSU_REJECT_LHS ] = { /* 647 */
+	.pme_name = "PM_LSU_REJECT_LHS",
+	.pme_code = 0x000004E05C,
+	.pme_short_desc = "LSU Reject due to LHS (up to 4 per cycle)",
+	.pme_long_desc = "LSU Reject due to LHS (up to 4 per cycle)",
+},
+[ POWER9_PME_PM_IPTEG_FROM_L3_MEPF ] = { /* 648 */
+	.pme_name = "PM_IPTEG_FROM_L3_MEPF",
+	.pme_code = 0x0000025042,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_LMEM ] = { /* 649 */
+	.pme_name = "PM_MRK_DATA_FROM_LMEM",
+	.pme_code = 0x000003D142,
+	.pme_short_desc = "The processor's data cache was reloaded from the local chip's Memory due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded from the local chip's Memory due to a marked load",
+},
+[ POWER9_PME_PM_L3_P1_CO_MEM ] = { /* 650 */
+	.pme_name = "PM_L3_P1_CO_MEM",
+	.pme_code = 0x00000368AA,
+	.pme_short_desc = "l3 CO to memory port 1",
+	.pme_long_desc = "l3 CO to memory port 1",
+},
+[ POWER9_PME_PM_FREQ_DOWN ] = { /* 651 */
+	.pme_name = "PM_FREQ_DOWN",
+	.pme_code = 0x000003000C,
+	.pme_short_desc = "Power Management: Below Threshold B",
+	.pme_long_desc = "Power Management: Below Threshold B",
+},
+[ POWER9_PME_PM_L3_CINJ ] = { /* 652 */
+	.pme_name = "PM_L3_CINJ",
+	.pme_code = 0x00000368A4,
+	.pme_short_desc = "l3 ci of cache inject",
+	.pme_long_desc = "l3 ci of cache inject",
+},
+[ POWER9_PME_PM_L3_P0_PF_RTY ] = { /* 653 */
+	.pme_name = "PM_L3_P0_PF_RTY",
+	.pme_code = 0x00000260AE,
+	.pme_short_desc = "L3 PF received retry port 2",
+	.pme_long_desc = "L3 PF received retry port 2",
+},
+[ POWER9_PME_PM_IPTEG_FROM_DL2L3_MOD ] = { /* 654 */
+	.pme_name = "PM_IPTEG_FROM_DL2L3_MOD",
+	.pme_code = 0x0000045048,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request",
+},
+[ POWER9_PME_PM_MRK_INST_ISSUED ] = { /* 655 */
+	.pme_name = "PM_MRK_INST_ISSUED",
+	.pme_code = 0x0000010132,
+	.pme_short_desc = "Marked instruction issued",
+	.pme_long_desc = "Marked instruction issued",
+},
+[ POWER9_PME_PM_INST_FROM_RL2L3_SHR ] = { /* 656 */
+	.pme_name = "PM_INST_FROM_RL2L3_SHR",
+	.pme_code = 0x000001404A,
+	.pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_LSU_STCX_FAIL ] = { /* 657 */
+	.pme_name = "PM_LSU_STCX_FAIL",
+	.pme_code = 0x000000F080,
+	.pme_short_desc = "stcx failed",
+	.pme_long_desc = "stcx failed",
+},
+[ POWER9_PME_PM_L3_P1_NODE_PUMP ] = { /* 658 */
+	.pme_name = "PM_L3_P1_NODE_PUMP",
+	.pme_code = 0x00000168B0,
+	.pme_short_desc = "L3 pf sent with nodal scope port 1",
+	.pme_long_desc = "L3 pf sent with nodal scope port 1",
+},
+[ POWER9_PME_PM_MEM_RWITM ] = { /* 659 */
+	.pme_name = "PM_MEM_RWITM",
+	.pme_code = 0x000003C05E,
+	.pme_short_desc = "Memory Read With Intent to Modify for this thread",
+	.pme_long_desc = "Memory Read With Intent to Modify for this thread",
+},
+[ POWER9_PME_PM_DP_QP_FLOP_CMPL ] = { /* 660 */
+	.pme_name = "PM_DP_QP_FLOP_CMPL",
+	.pme_code = 0x000004D05C,
+	.pme_short_desc = "Double-precision flop instruction completed",
+	.pme_long_desc = "Double-precision flop instruction completed",
+},
+[ POWER9_PME_PM_RUN_PURR ] = { /* 661 */
+	.pme_name = "PM_RUN_PURR",
+	.pme_code = 0x00000400F4,
+	.pme_short_desc = "Run_PURR",
+	.pme_long_desc = "Run_PURR",
+},
+[ POWER9_PME_PM_CMPLU_STALL_LMQ_FULL ] = { /* 662 */
+	.pme_name = "PM_CMPLU_STALL_LMQ_FULL",
+	.pme_code = 0x000004C014,
+	.pme_short_desc = "Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full",
+	.pme_long_desc = "Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full",
+},
+[ POWER9_PME_PM_CMPLU_STALL_VDPLONG ] = { /* 663 */
+	.pme_name = "PM_CMPLU_STALL_VDPLONG",
+	.pme_code = 0x000003C05A,
+	.pme_short_desc = "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish.",
+	.pme_long_desc = "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Qualified by NOT vector AND multicycle",
+},
+[ POWER9_PME_PM_LSU2_TM_L1_HIT ] = { /* 664 */
+	.pme_name = "PM_LSU2_TM_L1_HIT",
+	.pme_code = 0x000000E098,
+	.pme_short_desc = "Load tm hit in L1",
+	.pme_long_desc = "Load tm hit in L1",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L3 ] = { /* 665 */
+	.pme_name = "PM_MRK_DATA_FROM_L3",
+	.pme_code = 0x000004D142,
+	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 due to a marked load",
+},
+[ POWER9_PME_PM_CMPLU_STALL_MTFPSCR ] = { /* 666 */
+	.pme_name = "PM_CMPLU_STALL_MTFPSCR",
+	.pme_code = 0x000004E012,
+	.pme_short_desc = "Completion stall because the ISU is updating the register and notifying the Effective Address Table (EAT)",
+	.pme_long_desc = "Completion stall because the ISU is updating the register and notifying the Effective Address Table (EAT)",
+},
+[ POWER9_PME_PM_STALL_END_ICT_EMPTY ] = { /* 667 */
+	.pme_name = "PM_STALL_END_ICT_EMPTY",
+	.pme_code = 0x0000010028,
+	.pme_short_desc = "The number a times the core transitioned from a stall to ICT-empty for this thread",
+	.pme_long_desc = "The number a times the core transitioned from a stall to ICT-empty for this thread",
+},
+[ POWER9_PME_PM_L3_P1_CO_L31 ] = { /* 668 */
+	.pme_name = "PM_L3_P1_CO_L31",
+	.pme_code = 0x00000468AA,
+	.pme_short_desc = "l3 CO to L3.",
+	.pme_long_desc = "l3 CO to L3.1 (lco) port 1",
+},
+[ POWER9_PME_PM_CMPLU_STALL_DCACHE_MISS ] = { /* 669 */
+	.pme_name = "PM_CMPLU_STALL_DCACHE_MISS",
+	.pme_code = 0x000002C012,
+	.pme_short_desc = "Finish stall because the NTF instruction was a load that missed the L1 and was waiting for the data to return from the nest",
+	.pme_long_desc = "Finish stall because the NTF instruction was a load that missed the L1 and was waiting for the data to return from the nest",
+},
+[ POWER9_PME_PM_DPTEG_FROM_DL2L3_MOD ] = { /* 670 */
+	.pme_name = "PM_DPTEG_FROM_DL2L3_MOD",
+	.pme_code = 0x000004E048,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_INST_FROM_L3_MEPF ] = { /* 671 */
+	.pme_name = "PM_INST_FROM_L3_MEPF",
+	.pme_code = 0x0000024042,
+	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state.",
+	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_L1_DCACHE_RELOADED_ALL ] = { /* 672 */
+	.pme_name = "PM_L1_DCACHE_RELOADED_ALL",
+	.pme_code = 0x000001002C,
+	.pme_short_desc = "L1 data cache reloaded for demand.",
+	.pme_long_desc = "L1 data cache reloaded for demand. If MMCR1[16] is 1, prefetches will be included as well",
+},
+[ POWER9_PME_PM_DATA_GRP_PUMP_CPRED ] = { /* 673 */
+	.pme_name = "PM_DATA_GRP_PUMP_CPRED",
+	.pme_code = 0x000002C050,
+	.pme_short_desc = "Initial and Final Pump Scope was group pump (prediction=correct) for a demand load",
+	.pme_long_desc = "Initial and Final Pump Scope was group pump (prediction=correct) for a demand load",
+},
+[ POWER9_PME_PM_MRK_DERAT_MISS_64K ] = { /* 674 */
+	.pme_name = "PM_MRK_DERAT_MISS_64K",
+	.pme_code = 0x000002D154,
+	.pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 64K",
+	.pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 64K",
+},
+[ POWER9_PME_PM_L2_ST_MISS ] = { /* 675 */
+	.pme_name = "PM_L2_ST_MISS",
+	.pme_code = 0x0000026880,
+	.pme_short_desc = "All successful D-Side Store dispatches that were an L2miss for this thread",
+	.pme_long_desc = "All successful D-Side Store dispatches that were an L2miss for this thread",
+},
+[ POWER9_PME_PM_L3_PF_OFF_CHIP_CACHE ] = { /* 676 */
+	.pme_name = "PM_L3_PF_OFF_CHIP_CACHE",
+	.pme_code = 0x00000368A0,
+	.pme_short_desc = "L3 Prefetch from Off chip cache",
+	.pme_long_desc = "L3 Prefetch from Off chip cache",
+},
+[ POWER9_PME_PM_RADIX_PWC_L3_PTE_FROM_L3MISS ] = { /* 677 */
+	.pme_name = "PM_RADIX_PWC_L3_PTE_FROM_L3MISS",
+	.pme_code = 0x000004F05E,
+	.pme_short_desc = "A Page Table Entry was reloaded to a level 3 page walk cache from beyond the core's L3 data cache.",
+	.pme_long_desc = "A Page Table Entry was reloaded to a level 3 page walk cache from beyond the core's L3 data cache. This implies that a level 4 PWC access was not necessary for this translation. The source could be local/remote/distant memory or another core's cache",
+},
+[ POWER9_PME_PM_LWSYNC ] = { /* 678 */
+	.pme_name = "PM_LWSYNC",
+	.pme_code = 0x0000005894,
+	.pme_short_desc = "Lwsync instruction decoded and transferred",
+	.pme_long_desc = "Lwsync instruction decoded and transferred",
+},
+[ POWER9_PME_PM_LS3_UNALIGNED_LD ] = { /* 679 */
+	.pme_name = "PM_LS3_UNALIGNED_LD",
+	.pme_code = 0x000000C898,
+	.pme_short_desc = "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size.",
+	.pme_long_desc = "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty",
+},
+[ POWER9_PME_PM_L3_RD0_BUSY ] = { /* 680 */
+	.pme_name = "PM_L3_RD0_BUSY",
+	.pme_code = 0x00000468B4,
+	.pme_short_desc = "lifetime, sample of RD machine 0 valid",
+	.pme_long_desc = "lifetime, sample of RD machine 0 valid",
+},
+[ POWER9_PME_PM_LINK_STACK_CORRECT ] = { /* 681 */
+	.pme_name = "PM_LINK_STACK_CORRECT",
+	.pme_code = 0x00000058A0,
+	.pme_short_desc = "Link stack predicts right address",
+	.pme_long_desc = "Link stack predicts right address",
+},
+[ POWER9_PME_PM_MRK_DTLB_MISS ] = { /* 682 */
+	.pme_name = "PM_MRK_DTLB_MISS",
+	.pme_code = 0x00000401E4,
+	.pme_short_desc = "Marked dtlb miss",
+	.pme_long_desc = "Marked dtlb miss",
+},
+[ POWER9_PME_PM_INST_IMC_MATCH_CMPL ] = { /* 683 */
+	.pme_name = "PM_INST_IMC_MATCH_CMPL",
+	.pme_code = 0x000004001C,
+	.pme_short_desc = "IMC Match Count",
+	.pme_long_desc = "IMC Match Count",
+},
+[ POWER9_PME_PM_LS1_ERAT_MISS_PREF ] = { /* 684 */
+	.pme_name = "PM_LS1_ERAT_MISS_PREF",
+	.pme_code = 0x000000E884,
+	.pme_short_desc = "LS1 Erat miss due to prefetch",
+	.pme_long_desc = "LS1 Erat miss due to prefetch",
+},
+[ POWER9_PME_PM_L3_CO0_BUSY ] = { /* 685 */
+	.pme_name = "PM_L3_CO0_BUSY",
+	.pme_code = 0x00000468AC,
+	.pme_short_desc = "lifetime, sample of CO machine 0 valid",
+	.pme_long_desc = "lifetime, sample of CO machine 0 valid",
+},
+[ POWER9_PME_PM_BFU_BUSY ] = { /* 686 */
+	.pme_name = "PM_BFU_BUSY",
+	.pme_code = 0x000003005C,
+	.pme_short_desc = "Cycles in which all 4 Binary Floating Point units are busy.",
+	.pme_long_desc = "Cycles in which all 4 Binary Floating Point units are busy. The BFU is running at capacity",
+},
+[ POWER9_PME_PM_L2_SYS_GUESS_CORRECT ] = { /* 687 */
+	.pme_name = "PM_L2_SYS_GUESS_CORRECT",
+	.pme_code = 0x0000036088,
+	.pme_short_desc = "L2 guess sys and guess was correct (ie data beyond-6chip)",
+	.pme_long_desc = "L2 guess sys and guess was correct (ie data beyond-6chip)",
+},
+[ POWER9_PME_PM_L1_SW_PREF ] = { /* 688 */
+	.pme_name = "PM_L1_SW_PREF",
+	.pme_code = 0x000000E880,
+	.pme_short_desc = "Software L1 Prefetches, including SW Transient Prefetches",
+	.pme_long_desc = "Software L1 Prefetches, including SW Transient Prefetches",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_LL4 ] = { /* 689 */
+	.pme_name = "PM_MRK_DATA_FROM_LL4",
+	.pme_code = 0x000001D14C,
+	.pme_short_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to a marked load",
+},
+[ POWER9_PME_PM_MRK_INST_FIN ] = { /* 690 */
+	.pme_name = "PM_MRK_INST_FIN",
+	.pme_code = 0x0000030130,
+	.pme_short_desc = "marked instruction finished",
+	.pme_long_desc = "marked instruction finished",
+},
+[ POWER9_PME_PM_SYNC_MRK_L3MISS ] = { /* 691 */
+	.pme_name = "PM_SYNC_MRK_L3MISS",
+	.pme_code = 0x0000015154,
+	.pme_short_desc = "Marked L3 misses that can throw a synchronous interrupt",
+	.pme_long_desc = "Marked L3 misses that can throw a synchronous interrupt",
+},
+[ POWER9_PME_PM_LSU1_STORE_REJECT ] = { /* 692 */
+	.pme_name = "PM_LSU1_STORE_REJECT",
+	.pme_code = 0x000000F88C,
+	.pme_short_desc = "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met",
+	.pme_long_desc = "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met",
+},
+[ POWER9_PME_PM_CHIP_PUMP_CPRED ] = { /* 693 */
+	.pme_name = "PM_CHIP_PUMP_CPRED",
+	.pme_code = 0x0000010050,
+	.pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
+	.pme_long_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC ] = { /* 694 */
+	.pme_name = "PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC",
+	.pme_code = 0x000001D14E,
+	.pme_short_desc = "Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load",
+},
+[ POWER9_PME_PM_DATA_STORE ] = { /* 695 */
+	.pme_name = "PM_DATA_STORE",
+	.pme_code = 0x000000F0A0,
+	.pme_short_desc = "All ops that drain from s2q to L2 containing data",
+	.pme_long_desc = "All ops that drain from s2q to L2 containing data",
+},
+[ POWER9_PME_PM_LS1_UNALIGNED_LD ] = { /* 696 */
+	.pme_name = "PM_LS1_UNALIGNED_LD",
+	.pme_code = 0x000000C894,
+	.pme_short_desc = "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size.",
+	.pme_long_desc = "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty",
+},
+[ POWER9_PME_PM_TM_TRANS_RUN_INST ] = { /* 697 */
+	.pme_name = "PM_TM_TRANS_RUN_INST",
+	.pme_code = 0x0000030060,
+	.pme_short_desc = "Run instructions completed in transactional state (gated by the run latch)",
+	.pme_long_desc = "Run instructions completed in transactional state (gated by the run latch)",
+},
+[ POWER9_PME_PM_IC_MISS_CMPL ] = { /* 698 */
+	.pme_name = "PM_IC_MISS_CMPL",
+	.pme_code = 0x000001D15A,
+	.pme_short_desc = "Non-speculative icache miss, counted at completion",
+	.pme_long_desc = "Non-speculative icache miss, counted at completion",
+},
+[ POWER9_PME_PM_THRESH_NOT_MET ] = { /* 699 */
+	.pme_name = "PM_THRESH_NOT_MET",
+	.pme_code = 0x000004016E,
+	.pme_short_desc = "Threshold counter did not meet threshold",
+	.pme_long_desc = "Threshold counter did not meet threshold",
+},
+[ POWER9_PME_PM_DPTEG_FROM_L2 ] = { /* 700 */
+	.pme_name = "PM_DPTEG_FROM_L2",
+	.pme_code = 0x000001E042,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_IPTEG_FROM_RL2L3_SHR ] = { /* 701 */
+	.pme_name = "PM_IPTEG_FROM_RL2L3_SHR",
+	.pme_code = 0x000001504A,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request",
+},
+[ POWER9_PME_PM_DPTEG_FROM_RMEM ] = { /* 702 */
+	.pme_name = "PM_DPTEG_FROM_RMEM",
+	.pme_code = 0x000003E04A,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_L3_L2_CO_MISS ] = { /* 703 */
+	.pme_name = "PM_L3_L2_CO_MISS",
+	.pme_code = 0x00000368A2,
+	.pme_short_desc = "L2 castout miss",
+	.pme_long_desc = "L2 castout miss",
+},
+[ POWER9_PME_PM_IPTEG_FROM_DMEM ] = { /* 704 */
+	.pme_name = "PM_IPTEG_FROM_DMEM",
+	.pme_code = 0x000004504C,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a instruction side request",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a instruction side request",
+},
+[ POWER9_PME_PM_MRK_DTLB_MISS_64K ] = { /* 705 */
+	.pme_name = "PM_MRK_DTLB_MISS_64K",
+	.pme_code = 0x000003D156,
+	.pme_short_desc = "Marked Data TLB Miss page size 64K",
+	.pme_long_desc = "Marked Data TLB Miss page size 64K",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC ] = { /* 706 */
+	.pme_name = "PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC",
+	.pme_code = 0x000002C122,
+	.pme_short_desc = "Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load",
+},
+[ POWER9_PME_PM_LSU_FIN ] = { /* 707 */
+	.pme_name = "PM_LSU_FIN",
+	.pme_code = 0x0000030066,
+	.pme_short_desc = "LSU Finished a PPC instruction (up to 4 per cycle)",
+	.pme_long_desc = "LSU Finished a PPC instruction (up to 4 per cycle)",
+},
+[ POWER9_PME_PM_DATA_FROM_L2_DISP_CONFLICT_OTHER ] = { /* 708 */
+	.pme_name = "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER",
+	.pme_code = 0x000004C040,
+	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_ON_CHIP_CACHE ] = { /* 709 */
+	.pme_name = "PM_MRK_DATA_FROM_ON_CHIP_CACHE",
+	.pme_code = 0x000004D140,
+	.pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load",
+},
+[ POWER9_PME_PM_LSU_STCX ] = { /* 710 */
+	.pme_name = "PM_LSU_STCX",
+	.pme_code = 0x000000C090,
+	.pme_short_desc = "STCX sent to nest, i.",
+	.pme_long_desc = "STCX sent to nest, i.e. total",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L2_1_MOD ] = { /* 711 */
+	.pme_name = "PM_MRK_DATA_FROM_L2_1_MOD",
+	.pme_code = 0x000004D146,
+	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a marked load",
+},
+[ POWER9_PME_PM_VSU_NON_FLOP_CMPL ] = { /* 712 */
+	.pme_name = "PM_VSU_NON_FLOP_CMPL",
+	.pme_code = 0x000004D050,
+	.pme_short_desc = "",
+	.pme_long_desc = "",
+},
+[ POWER9_PME_PM_INST_FROM_L3_DISP_CONFLICT ] = { /* 713 */
+	.pme_name = "PM_INST_FROM_L3_DISP_CONFLICT",
+	.pme_code = 0x0000034042,
+	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L2_1_SHR ] = { /* 714 */
+	.pme_name = "PM_MRK_DATA_FROM_L2_1_SHR",
+	.pme_code = 0x000002D14E,
+	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a marked load",
+},
+[ POWER9_PME_PM_RADIX_PWC_L4_PTE_FROM_L3 ] = { /* 715 */
+	.pme_name = "PM_RADIX_PWC_L4_PTE_FROM_L3",
+	.pme_code = 0x000004F05A,
+	.pme_short_desc = "A Page Table Entry was reloaded to a level 4 page walk cache from the core's L3 data cache.",
+	.pme_long_desc = "A Page Table Entry was reloaded to a level 4 page walk cache from the core's L3 data cache. This is the deepest level of PWC possible for a translation",
+},
+[ POWER9_PME_PM_TAGE_CORRECT ] = { /* 716 */
+	.pme_name = "PM_TAGE_CORRECT",
+	.pme_code = 0x00000058B4,
+	.pme_short_desc = "The TAGE overrode BHT direction prediction and it was correct.",
+	.pme_long_desc = "The TAGE overrode BHT direction prediction and it was correct. Includes taken and not taken and is counted at execution time",
+},
+[ POWER9_PME_PM_TM_FAV_CAUSED_FAIL ] = { /* 717 */
+	.pme_name = "PM_TM_FAV_CAUSED_FAIL",
+	.pme_code = 0x000002688C,
+	.pme_short_desc = "TM Load (fav) caused another thread to fail",
+	.pme_long_desc = "TM Load (fav) caused another thread to fail",
+},
+[ POWER9_PME_PM_RADIX_PWC_L1_HIT ] = { /* 718 */
+	.pme_name = "PM_RADIX_PWC_L1_HIT",
+	.pme_code = 0x000001F056,
+	.pme_short_desc = "A radix translation attempt missed in the TLB and only the first level page walk cache was a hit.",
+	.pme_long_desc = "A radix translation attempt missed in the TLB and only the first level page walk cache was a hit.",
+},
+[ POWER9_PME_PM_LSU0_LMQ_S0_VALID ] = { /* 719 */
+	.pme_name = "PM_LSU0_LMQ_S0_VALID",
+	.pme_code = 0x000000D8B8,
+	.pme_short_desc = "Slot 0 of LMQ valid",
+	.pme_long_desc = "Slot 0 of LMQ valid",
+},
+[ POWER9_PME_PM_BR_MPRED_CCACHE ] = { /* 720 */
+	.pme_name = "PM_BR_MPRED_CCACHE",
+	.pme_code = 0x00000040AC,
+	.pme_short_desc = "Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction",
+	.pme_long_desc = "Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction",
+},
+[ POWER9_PME_PM_L1_DEMAND_WRITE ] = { /* 721 */
+	.pme_name = "PM_L1_DEMAND_WRITE",
+	.pme_code = 0x000000408C,
+	.pme_short_desc = "Instruction Demand sectors wriittent into IL1",
+	.pme_long_desc = "Instruction Demand sectors wriittent into IL1",
+},
+[ POWER9_PME_PM_CMPLU_STALL_FLUSH_ANY_THREAD ] = { /* 722 */
+	.pme_name = "PM_CMPLU_STALL_FLUSH_ANY_THREAD",
+	.pme_code = 0x000001E056,
+	.pme_short_desc = "Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion",
+	.pme_long_desc = "Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion",
+},
+[ POWER9_PME_PM_IPTEG_FROM_L3MISS ] = { /* 723 */
+	.pme_name = "PM_IPTEG_FROM_L3MISS",
+	.pme_code = 0x000004504E,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a instruction side request",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a instruction side request",
+},
+[ POWER9_PME_PM_MRK_DTLB_MISS_16G ] = { /* 724 */
+	.pme_name = "PM_MRK_DTLB_MISS_16G",
+	.pme_code = 0x000002D15E,
+	.pme_short_desc = "Marked Data TLB Miss page size 16G",
+	.pme_long_desc = "Marked Data TLB Miss page size 16G",
+},
+[ POWER9_PME_PM_IPTEG_FROM_RL4 ] = { /* 725 */
+	.pme_name = "PM_IPTEG_FROM_RL4",
+	.pme_code = 0x000002504A,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request",
+},
+[ POWER9_PME_PM_L2_RCST_DISP ] = { /* 726 */
+	.pme_name = "PM_L2_RCST_DISP",
+	.pme_code = 0x0000036084,
+	.pme_short_desc = "L2 RC store dispatch attempt",
+	.pme_long_desc = "L2 RC store dispatch attempt",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC ] = { /* 727 */
+	.pme_name = "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC",
+	.pme_code = 0x000003D140,
+	.pme_short_desc = "Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load",
+},
+[ POWER9_PME_PM_CMPLU_STALL ] = { /* 728 */
+	.pme_name = "PM_CMPLU_STALL",
+	.pme_code = 0x000001E054,
+	.pme_short_desc = "Nothing completed and ICT not empty",
+	.pme_long_desc = "Nothing completed and ICT not empty",
+},
+[ POWER9_PME_PM_DISP_CLB_HELD_SB ] = { /* 729 */
+	.pme_name = "PM_DISP_CLB_HELD_SB",
+	.pme_code = 0x0000002090,
+	.pme_short_desc = "Dispatch/CLB Hold: Scoreboard",
+	.pme_long_desc = "Dispatch/CLB Hold: Scoreboard",
+},
+[ POWER9_PME_PM_L3_SN_USAGE ] = { /* 730 */
+	.pme_name = "PM_L3_SN_USAGE",
+	.pme_code = 0x00000160AC,
+	.pme_short_desc = "rotating sample of 8 snoop valids",
+	.pme_long_desc = "rotating sample of 8 snoop valids",
+},
+[ POWER9_PME_PM_FLOP_CMPL ] = { /* 731 */
+	.pme_name = "PM_FLOP_CMPL",
+	.pme_code = 0x00000100F4,
+	.pme_short_desc = "Floating Point Operation Finished",
+	.pme_long_desc = "Floating Point Operation Finished",
+},
+[ POWER9_PME_PM_MRK_L2_RC_DISP ] = { /* 732 */
+	.pme_name = "PM_MRK_L2_RC_DISP",
+	.pme_code = 0x0000020114,
+	.pme_short_desc = "Marked Instruction RC dispatched in L2",
+	.pme_long_desc = "Marked Instruction RC dispatched in L2",
+},
+[ POWER9_PME_PM_L3_PF_ON_CHIP_CACHE ] = { /* 733 */
+	.pme_name = "PM_L3_PF_ON_CHIP_CACHE",
+	.pme_code = 0x00000360A0,
+	.pme_short_desc = "L3 Prefetch from On chip cache",
+	.pme_long_desc = "L3 Prefetch from On chip cache",
+},
+[ POWER9_PME_PM_IC_DEMAND_CYC ] = { /* 734 */
+	.pme_name = "PM_IC_DEMAND_CYC",
+	.pme_code = 0x0000010018,
+	.pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load",
+	.pme_long_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load",
+},
+[ POWER9_PME_PM_CO_USAGE ] = { /* 735 */
+	.pme_name = "PM_CO_USAGE",
+	.pme_code = 0x000002688E,
+	.pme_short_desc = " continuous 16 cycle(2to1) window where this signals rotates thru sampling each machine",
+	.pme_long_desc = " continuous 16 cycle(2to1) window where this signals rotates thru sampling each machine",
+},
+[ POWER9_PME_PM_ISYNC ] = { /* 736 */
+	.pme_name = "PM_ISYNC",
+	.pme_code = 0x0000002884,
+	.pme_short_desc = "Isync completion count per thread",
+	.pme_long_desc = "Isync completion count per thread",
+},
+[ POWER9_PME_PM_MEM_CO ] = { /* 737 */
+	.pme_name = "PM_MEM_CO",
+	.pme_code = 0x000004C058,
+	.pme_short_desc = "Memory castouts from this thread",
+	.pme_long_desc = "Memory castouts from this thread",
+},
+[ POWER9_PME_PM_NTC_ALL_FIN ] = { /* 738 */
+	.pme_name = "PM_NTC_ALL_FIN",
+	.pme_code = 0x000002001A,
+	.pme_short_desc = "Cycles after all instructions have finished to group completed",
+	.pme_long_desc = "Cycles after all instructions have finished to group completed",
+},
+[ POWER9_PME_PM_CMPLU_STALL_EXCEPTION ] = { /* 739 */
+	.pme_name = "PM_CMPLU_STALL_EXCEPTION",
+	.pme_code = 0x000003003A,
+	.pme_short_desc = "Cycles in which the NTC instruction is not allowed to complete because it was interrupted by ANY exception, which has to be serviced before the instruction can complete",
+	.pme_long_desc = "Cycles in which the NTC instruction is not allowed to complete because it was interrupted by ANY exception, which has to be serviced before the instruction can complete",
+},
+[ POWER9_PME_PM_LS0_LAUNCH_HELD_PREF ] = { /* 740 */
+	.pme_name = "PM_LS0_LAUNCH_HELD_PREF",
+	.pme_code = 0x000000C09C,
+	.pme_short_desc = "Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle",
+	.pme_long_desc = "Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle",
+},
+[ POWER9_PME_PM_ICT_NOSLOT_BR_MPRED ] = { /* 741 */
+	.pme_name = "PM_ICT_NOSLOT_BR_MPRED",
+	.pme_code = 0x000004D01E,
+	.pme_short_desc = "Ict empty for this thread due to branch mispred",
+	.pme_long_desc = "Ict empty for this thread due to branch mispred",
+},
+[ POWER9_PME_PM_MRK_BR_CMPL ] = { /* 742 */
+	.pme_name = "PM_MRK_BR_CMPL",
+	.pme_code = 0x000001016E,
+	.pme_short_desc = "Branch Instruction completed",
+	.pme_long_desc = "Branch Instruction completed",
+},
+[ POWER9_PME_PM_ICT_NOSLOT_DISP_HELD ] = { /* 743 */
+	.pme_name = "PM_ICT_NOSLOT_DISP_HELD",
+	.pme_code = 0x000004E01A,
+	.pme_short_desc = "Cycles in which the NTC instruciton is held at dispatch for any reason",
+	.pme_long_desc = "Cycles in which the NTC instruciton is held at dispatch for any reason",
+},
+[ POWER9_PME_PM_IC_PREF_WRITE ] = { /* 744 */
+	.pme_name = "PM_IC_PREF_WRITE",
+	.pme_code = 0x000000488C,
+	.pme_short_desc = "Instruction prefetch written into IL1",
+	.pme_long_desc = "Instruction prefetch written into IL1",
+},
+[ POWER9_PME_PM_MRK_LSU_FLUSH_LHL_SHL ] = { /* 745 */
+	.pme_name = "PM_MRK_LSU_FLUSH_LHL_SHL",
+	.pme_code = 0x000000D8A0,
+	.pme_short_desc = "The instruction was flushed because of a sequential load/store consistency.",
+	.pme_long_desc = "The instruction was flushed because of a sequential load/store consistency. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores).",
+},
+[ POWER9_PME_PM_DTLB_MISS_1G ] = { /* 746 */
+	.pme_name = "PM_DTLB_MISS_1G",
+	.pme_code = 0x000004C05A,
+	.pme_short_desc = "Data TLB reload (after a miss) page size 1G.",
+	.pme_long_desc = "Data TLB reload (after a miss) page size 1G. Implies radix translation was used",
+},
+[ POWER9_PME_PM_DATA_FROM_L2_NO_CONFLICT ] = { /* 747 */
+	.pme_name = "PM_DATA_FROM_L2_NO_CONFLICT",
+	.pme_code = 0x000001C040,
+	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_L3MISS ] = { /* 748 */
+	.pme_name = "PM_MRK_DPTEG_FROM_L3MISS",
+	.pme_code = 0x000004F14E,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a marked data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_BR_PRED ] = { /* 749 */
+	.pme_name = "PM_BR_PRED",
+	.pme_code = 0x000000409C,
+	.pme_short_desc = "Conditional Branch Executed in which the HW predicted the Direction or Target.",
+	.pme_long_desc = "Conditional Branch Executed in which the HW predicted the Direction or Target. Includes taken and not taken and is counted at execution time",
+},
+[ POWER9_PME_PM_CMPLU_STALL_OTHER_CMPL ] = { /* 750 */
+	.pme_name = "PM_CMPLU_STALL_OTHER_CMPL",
+	.pme_code = 0x0000030006,
+	.pme_short_desc = "Instructions the core completed while this tread was stalled",
+	.pme_long_desc = "Instructions the core completed while this tread was stalled",
+},
+[ POWER9_PME_PM_INST_FROM_DMEM ] = { /* 751 */
+	.pme_name = "PM_INST_FROM_DMEM",
+	.pme_code = 0x000004404C,
+	.pme_short_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_L2_NO_CONFLICT ] = { /* 752 */
+	.pme_name = "PM_MRK_DPTEG_FROM_L2_NO_CONFLICT",
+	.pme_code = 0x000001F140,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_DC_PREF_SW_ALLOC ] = { /* 753 */
+	.pme_name = "PM_DC_PREF_SW_ALLOC",
+	.pme_code = 0x000000F8A4,
+	.pme_short_desc = "Prefetch stream allocated by software prefetching",
+	.pme_long_desc = "Prefetch stream allocated by software prefetching",
+},
+[ POWER9_PME_PM_L2_RCST_DISP_FAIL_OTHER ] = { /* 754 */
+	.pme_name = "PM_L2_RCST_DISP_FAIL_OTHER",
+	.pme_code = 0x0000046084,
+	.pme_short_desc = "L2 RC store dispatch attempt failed due to other reasons",
+	.pme_long_desc = "L2 RC store dispatch attempt failed due to other reasons",
+},
+[ POWER9_PME_PM_CMPLU_STALL_EMQ_FULL ] = { /* 755 */
+	.pme_name = "PM_CMPLU_STALL_EMQ_FULL",
+	.pme_code = 0x0000030004,
+	.pme_short_desc = "Finish stall because the next to finish instruction suffered an ERAT miss and the EMQ was full",
+	.pme_long_desc = "Finish stall because the next to finish instruction suffered an ERAT miss and the EMQ was full",
+},
+[ POWER9_PME_PM_MRK_INST_DECODED ] = { /* 756 */
+	.pme_name = "PM_MRK_INST_DECODED",
+	.pme_code = 0x0000020130,
+	.pme_short_desc = "An instruction was marked at decode time.",
+	.pme_long_desc = "An instruction was marked at decode time. Random Instruction Sampling (RIS) only",
+},
+[ POWER9_PME_PM_IERAT_RELOAD_4K ] = { /* 757 */
+	.pme_name = "PM_IERAT_RELOAD_4K",
+	.pme_code = 0x0000020064,
+	.pme_short_desc = "IERAT reloaded (after a miss) for 4K pages",
+	.pme_long_desc = "IERAT reloaded (after a miss) for 4K pages",
+},
+[ POWER9_PME_PM_CMPLU_STALL_LRQ_OTHER ] = { /* 758 */
+	.pme_name = "PM_CMPLU_STALL_LRQ_OTHER",
+	.pme_code = 0x0000010004,
+	.pme_short_desc = "Finish stall due to LRQ miscellaneous reasons, lost arbitration to LMQ slot, bank collisions, set prediction cleanup, set prediction multihit and others",
+	.pme_long_desc = "Finish stall due to LRQ miscellaneous reasons, lost arbitration to LMQ slot, bank collisions, set prediction cleanup, set prediction multihit and others",
+},
+[ POWER9_PME_PM_INST_FROM_L3_1_ECO_MOD ] = { /* 759 */
+	.pme_name = "PM_INST_FROM_L3_1_ECO_MOD",
+	.pme_code = 0x0000044044,
+	.pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_L3_P0_CO_L31 ] = { /* 760 */
+	.pme_name = "PM_L3_P0_CO_L31",
+	.pme_code = 0x00000460AA,
+	.pme_short_desc = "l3 CO to L3.",
+	.pme_long_desc = "l3 CO to L3.1 (lco) port 0",
+},
+[ POWER9_PME_PM_NON_TM_RST_SC ] = { /* 761 */
+	.pme_name = "PM_NON_TM_RST_SC",
+	.pme_code = 0x00000260A6,
+	.pme_short_desc = "non tm snp rst tm sc",
+	.pme_long_desc = "non tm snp rst tm sc",
+},
+[ POWER9_PME_PM_RADIX_PWC_L4_PTE_FROM_L2 ] = { /* 762 */
+	.pme_name = "PM_RADIX_PWC_L4_PTE_FROM_L2",
+	.pme_code = 0x000001F05A,
+	.pme_short_desc = "A Page Table Entry was reloaded to a level 4 page walk cache from the core's L2 data cache.",
+	.pme_long_desc = "A Page Table Entry was reloaded to a level 4 page walk cache from the core's L2 data cache. This is the deepest level of PWC possible for a translation",
+},
+[ POWER9_PME_PM_INST_SYS_PUMP_CPRED ] = { /* 763 */
+	.pme_name = "PM_INST_SYS_PUMP_CPRED",
+	.pme_code = 0x0000034050,
+	.pme_short_desc = "Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch",
+	.pme_long_desc = "Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch",
+},
+[ POWER9_PME_PM_DPTEG_FROM_DMEM ] = { /* 764 */
+	.pme_name = "PM_DPTEG_FROM_DMEM",
+	.pme_code = 0x000004E04C,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { /* 765 */
+	.pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC",
+	.pme_code = 0x000002003E,
+	.pme_short_desc = "Cycles in which the LSU is empty for all threads (lmq and srq are completely empty)",
+	.pme_long_desc = "Cycles in which the LSU is empty for all threads (lmq and srq are completely empty)",
+},
+[ POWER9_PME_PM_SYS_PUMP_CPRED ] = { /* 766 */
+	.pme_name = "PM_SYS_PUMP_CPRED",
+	.pme_code = 0x0000030050,
+	.pme_short_desc = "Initial and Final Pump Scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
+	.pme_long_desc = "Initial and Final Pump Scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
+},
+[ POWER9_PME_PM_DTLB_MISS_64K ] = { /* 767 */
+	.pme_name = "PM_DTLB_MISS_64K",
+	.pme_code = 0x000003C056,
+	.pme_short_desc = "Data TLB Miss page size 64K",
+	.pme_long_desc = "Data TLB Miss page size 64K",
+},
+[ POWER9_PME_PM_CMPLU_STALL_STCX ] = { /* 768 */
+	.pme_name = "PM_CMPLU_STALL_STCX",
+	.pme_code = 0x000002D01C,
+	.pme_short_desc = "Finish stall because the NTF instruction was a stcx waiting for response from L2",
+	.pme_long_desc = "Finish stall because the NTF instruction was a stcx waiting for response from L2",
+},
+[ POWER9_PME_PM_MRK_FAB_RSP_CLAIM_RTY ] = { /* 769 */
+	.pme_name = "PM_MRK_FAB_RSP_CLAIM_RTY",
+	.pme_code = 0x000003015E,
+	.pme_short_desc = "Sampled store did a rwitm and got a rty",
+	.pme_long_desc = "Sampled store did a rwitm and got a rty",
+},
+[ POWER9_PME_PM_PARTIAL_ST_FIN ] = { /* 770 */
+	.pme_name = "PM_PARTIAL_ST_FIN",
+	.pme_code = 0x0000034054,
+	.pme_short_desc = "Any store finished by an LSU slice",
+	.pme_long_desc = "Any store finished by an LSU slice",
+},
+[ POWER9_PME_PM_THRD_CONC_RUN_INST ] = { /* 771 */
+	.pme_name = "PM_THRD_CONC_RUN_INST",
+	.pme_code = 0x00000300F4,
+	.pme_short_desc = "PPC Instructions Finished by this thread when all threads in the core had the run-latch set",
+	.pme_long_desc = "PPC Instructions Finished by this thread when all threads in the core had the run-latch set",
+},
+[ POWER9_PME_PM_CO_TM_SC_FOOTPRINT ] = { /* 772 */
+	.pme_name = "PM_CO_TM_SC_FOOTPRINT",
+	.pme_code = 0x0000026086,
+	.pme_short_desc = "L2 did a cleanifdirty CO to the L3 (ie created an SC line in the L3)",
+	.pme_long_desc = "L2 did a cleanifdirty CO to the L3 (ie created an SC line in the L3)",
+},
+[ POWER9_PME_PM_MRK_LARX_FIN ] = { /* 773 */
+	.pme_name = "PM_MRK_LARX_FIN",
+	.pme_code = 0x0000040116,
+	.pme_short_desc = "Larx finished",
+	.pme_long_desc = "Larx finished",
+},
+[ POWER9_PME_PM_L3_LOC_GUESS_WRONG ] = { /* 774 */
+	.pme_name = "PM_L3_LOC_GUESS_WRONG",
+	.pme_code = 0x00000268B2,
+	.pme_short_desc = "Initial scope=node but data from out side local node (near or far or rem).",
+	.pme_long_desc = "Initial scope=node but data from out side local node (near or far or rem). Prediction too Low",
+},
+[ POWER9_PME_PM_CMPLU_STALL_DMISS_L21_L31 ] = { /* 775 */
+	.pme_name = "PM_CMPLU_STALL_DMISS_L21_L31",
+	.pme_code = 0x000002C018,
+	.pme_short_desc = "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)",
+	.pme_long_desc = "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)",
+},
+[ POWER9_PME_PM_SHL_ST_DISABLE ] = { /* 776 */
+	.pme_name = "PM_SHL_ST_DISABLE",
+	.pme_code = 0x0000005090,
+	.pme_short_desc = "Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to the entry shown to not prevent the flush)",
+	.pme_long_desc = "Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to the entry shown to not prevent the flush)",
+},
+[ POWER9_PME_PM_VSU_FIN ] = { /* 777 */
+	.pme_name = "PM_VSU_FIN",
+	.pme_code = 0x000002505C,
+	.pme_short_desc = "VSU instruction finished.",
+	.pme_long_desc = "VSU instruction finished. Up to 4 per cycle",
+},
+[ POWER9_PME_PM_MRK_LSU_FLUSH_ATOMIC ] = { /* 778 */
+	.pme_name = "PM_MRK_LSU_FLUSH_ATOMIC",
+	.pme_code = 0x000000D098,
+	.pme_short_desc = "Quad-word loads (lq) are considered atomic because they always span at least 2 slices.",
+	.pme_long_desc = "Quad-word loads (lq) are considered atomic because they always span at least 2 slices. If a snoop or store from another thread changes the data the load is accessing between the 2 or 3 pieces of the lq instruction, the lq will be flushed",
+},
+[ POWER9_PME_PM_L3_CI_HIT ] = { /* 779 */
+	.pme_name = "PM_L3_CI_HIT",
+	.pme_code = 0x00000260A2,
+	.pme_short_desc = "L3 Castins Hit (total count",
+	.pme_long_desc = "L3 Castins Hit (total count",
+},
+[ POWER9_PME_PM_CMPLU_STALL_DARQ ] = { /* 780 */
+	.pme_name = "PM_CMPLU_STALL_DARQ",
+	.pme_code = 0x000003405A,
+	.pme_short_desc = "Finish stall because the next to finish instruction was spending cycles in the DARQ.",
+	.pme_long_desc = "Finish stall because the next to finish instruction was spending cycles in the DARQ. If this count is large is likely because the LSAQ had less than 4 slots available",
+},
+[ POWER9_PME_PM_L3_PF_ON_CHIP_MEM ] = { /* 781 */
+	.pme_name = "PM_L3_PF_ON_CHIP_MEM",
+	.pme_code = 0x00000460A0,
+	.pme_short_desc = "L3 Prefetch from On chip memory",
+	.pme_long_desc = "L3 Prefetch from On chip memory",
+},
+[ POWER9_PME_PM_THRD_PRIO_0_1_CYC ] = { /* 782 */
+	.pme_name = "PM_THRD_PRIO_0_1_CYC",
+	.pme_code = 0x00000040BC,
+	.pme_short_desc = "Cycles thread running at priority level 0 or 1",
+	.pme_long_desc = "Cycles thread running at priority level 0 or 1",
+},
+[ POWER9_PME_PM_DERAT_MISS_64K ] = { /* 783 */
+	.pme_name = "PM_DERAT_MISS_64K",
+	.pme_code = 0x000002C054,
+	.pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 64K",
+	.pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 64K",
+},
+[ POWER9_PME_PM_PMC2_REWIND ] = { /* 784 */
+	.pme_name = "PM_PMC2_REWIND",
+	.pme_code = 0x0000030020,
+	.pme_short_desc = "PMC2 Rewind Event (did not match condition)",
+	.pme_long_desc = "PMC2 Rewind Event (did not match condition)",
+},
+[ POWER9_PME_PM_INST_FROM_L2 ] = { /* 785 */
+	.pme_name = "PM_INST_FROM_L2",
+	.pme_code = 0x0000014042,
+	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_MRK_NTF_FIN ] = { /* 786 */
+	.pme_name = "PM_MRK_NTF_FIN",
+	.pme_code = 0x0000020112,
+	.pme_short_desc = "Marked next to finish instruction finished",
+	.pme_long_desc = "Marked next to finish instruction finished",
+},
+[ POWER9_PME_PM_ALL_SRQ_FULL ] = { /* 787 */
+	.pme_name = "PM_ALL_SRQ_FULL",
+	.pme_code = 0x0000020004,
+	.pme_short_desc = "Number of cycles the SRQ is completely out of srq entries.",
+	.pme_long_desc = "Number of cycles the SRQ is completely out of srq entries. This event is not per thread, all threads will get the same count for this core resource",
+},
+[ POWER9_PME_PM_INST_DISP ] = { /* 788 */
+	.pme_name = "PM_INST_DISP",
+	.pme_code = 0x00000200F2,
+	.pme_short_desc = "# PPC Dispatched",
+	.pme_long_desc = "# PPC Dispatched",
+},
+[ POWER9_PME_PM_LS3_ERAT_MISS_PREF ] = { /* 789 */
+	.pme_name = "PM_LS3_ERAT_MISS_PREF",
+	.pme_code = 0x000000E888,
+	.pme_short_desc = "LS1 Erat miss due to prefetch",
+	.pme_long_desc = "LS1 Erat miss due to prefetch",
+},
+[ POWER9_PME_PM_STOP_FETCH_PENDING_CYC ] = { /* 790 */
+	.pme_name = "PM_STOP_FETCH_PENDING_CYC",
+	.pme_code = 0x00000048A4,
+	.pme_short_desc = "Fetching is stopped due to an incoming instruction that will result in a flush",
+	.pme_long_desc = "Fetching is stopped due to an incoming instruction that will result in a flush",
+},
+[ POWER9_PME_PM_L1_DCACHE_RELOAD_VALID ] = { /* 791 */
+	.pme_name = "PM_L1_DCACHE_RELOAD_VALID",
+	.pme_code = 0x00000300F6,
+	.pme_short_desc = "DL1 reloaded due to Demand Load",
+	.pme_long_desc = "DL1 reloaded due to Demand Load",
+},
+[ POWER9_PME_PM_L3_P0_LCO_NO_DATA ] = { /* 792 */
+	.pme_name = "PM_L3_P0_LCO_NO_DATA",
+	.pme_code = 0x00000160AA,
+	.pme_short_desc = "dataless l3 lco sent port 0",
+	.pme_long_desc = "dataless l3 lco sent port 0",
+},
+[ POWER9_PME_PM_LSU3_VECTOR_LD_FIN ] = { /* 793 */
+	.pme_name = "PM_LSU3_VECTOR_LD_FIN",
+	.pme_code = 0x000000C884,
+	.pme_short_desc = "A vector load instruction finished.",
+	.pme_long_desc = "A vector load instruction finished. The ops considered in this category are lxv*, lvx*, lve*, lxsi*zx, lxvwsx, lxsd, lxssp, lxvl, lxvll, lxvb16x, lxvh8x, lxv, lxvx",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_L3_NO_CONFLICT ] = { /* 794 */
+	.pme_name = "PM_MRK_DPTEG_FROM_L3_NO_CONFLICT",
+	.pme_code = 0x000001F144,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_MRK_FXU_FIN ] = { /* 795 */
+	.pme_name = "PM_MRK_FXU_FIN",
+	.pme_code = 0x0000020134,
+	.pme_short_desc = "fxu marked instr finish",
+	.pme_long_desc = "fxu marked instr finish",
+},
+[ POWER9_PME_PM_LS3_UNALIGNED_ST ] = { /* 796 */
+	.pme_name = "PM_LS3_UNALIGNED_ST",
+	.pme_code = 0x000000F8BC,
+	.pme_short_desc = "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size.",
+	.pme_long_desc = "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty",
+},
+[ POWER9_PME_PM_DPTEG_FROM_MEMORY ] = { /* 797 */
+	.pme_name = "PM_DPTEG_FROM_MEMORY",
+	.pme_code = 0x000002E04C,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_RUN_CYC_ST_MODE ] = { /* 798 */
+	.pme_name = "PM_RUN_CYC_ST_MODE",
+	.pme_code = 0x000001006C,
+	.pme_short_desc = "Cycles run latch is set and core is in ST mode",
+	.pme_long_desc = "Cycles run latch is set and core is in ST mode",
+},
+[ POWER9_PME_PM_PMC4_OVERFLOW ] = { /* 799 */
+	.pme_name = "PM_PMC4_OVERFLOW",
+	.pme_code = 0x0000010010,
+	.pme_short_desc = "Overflow from counter 4",
+	.pme_long_desc = "Overflow from counter 4",
+},
+[ POWER9_PME_PM_THRESH_EXC_256 ] = { /* 800 */
+	.pme_name = "PM_THRESH_EXC_256",
+	.pme_code = 0x00000101E8,
+	.pme_short_desc = "Threshold counter exceed a count of 256",
+	.pme_long_desc = "Threshold counter exceed a count of 256",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L3_1_ECO_MOD_CYC ] = { /* 801 */
+	.pme_name = "PM_MRK_DATA_FROM_L3_1_ECO_MOD_CYC",
+	.pme_code = 0x0000035158,
+	.pme_short_desc = "Duration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load",
+},
+[ POWER9_PME_PM_LSU0_LRQ_S0_VALID_CYC ] = { /* 802 */
+	.pme_name = "PM_LSU0_LRQ_S0_VALID_CYC",
+	.pme_code = 0x000000D8B4,
+	.pme_short_desc = "Slot 0 of LRQ valid",
+	.pme_long_desc = "Slot 0 of LRQ valid",
+},
+[ POWER9_PME_PM_INST_FROM_L2MISS ] = { /* 803 */
+	.pme_name = "PM_INST_FROM_L2MISS",
+	.pme_code = 0x000001404E,
+	.pme_short_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_MRK_L2_TM_ST_ABORT_SISTER ] = { /* 804 */
+	.pme_name = "PM_MRK_L2_TM_ST_ABORT_SISTER",
+	.pme_code = 0x000003E15C,
+	.pme_short_desc = "TM marked store abort for this thread",
+	.pme_long_desc = "TM marked store abort for this thread",
+},
+[ POWER9_PME_PM_L2_ST ] = { /* 805 */
+	.pme_name = "PM_L2_ST",
+	.pme_code = 0x0000016880,
+	.pme_short_desc = "All successful D-side store dispatches for this thread",
+	.pme_long_desc = "All successful D-side store dispatches for this thread",
+},
+[ POWER9_PME_PM_RADIX_PWC_MISS ] = { /* 806 */
+	.pme_name = "PM_RADIX_PWC_MISS",
+	.pme_code = 0x000004F054,
+	.pme_short_desc = "A radix translation attempt missed in the TLB and all levels of page walk cache.",
+	.pme_long_desc = "A radix translation attempt missed in the TLB and all levels of page walk cache.",
+},
+[ POWER9_PME_PM_MRK_ST_L2DISP_TO_CMPL_CYC ] = { /* 807 */
+	.pme_name = "PM_MRK_ST_L2DISP_TO_CMPL_CYC",
+	.pme_code = 0x000001F150,
+	.pme_short_desc = "cycles from L2 rc disp to l2 rc completion",
+	.pme_long_desc = "cycles from L2 rc disp to l2 rc completion",
+},
+[ POWER9_PME_PM_LSU1_LDMX_FIN ] = { /* 808 */
+	.pme_name = "PM_LSU1_LDMX_FIN",
+	.pme_code = 0x000000D888,
+	.pme_short_desc = " New P9 instruction LDMX.",
+	.pme_long_desc = " New P9 instruction LDMX.",
+},
+[ POWER9_PME_PM_L3_P2_LCO_RTY ] = { /* 809 */
+	.pme_name = "PM_L3_P2_LCO_RTY",
+	.pme_code = 0x00000260B4,
+	.pme_short_desc = "L3 lateral cast out received retry on port 2",
+	.pme_long_desc = "L3 lateral cast out received retry on port 2",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_DL2L3_SHR ] = { /* 810 */
+	.pme_name = "PM_MRK_DATA_FROM_DL2L3_SHR",
+	.pme_code = 0x000001D150,
+	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
+},
+[ POWER9_PME_PM_L2_GRP_GUESS_CORRECT ] = { /* 811 */
+	.pme_name = "PM_L2_GRP_GUESS_CORRECT",
+	.pme_code = 0x0000026088,
+	.pme_short_desc = "L2 guess grp and guess was correct (data intra-6chip AND ^on-chip)",
+	.pme_long_desc = "L2 guess grp and guess was correct (data intra-6chip AND ^on-chip)",
+},
+[ POWER9_PME_PM_LSU0_1_LRQF_FULL_CYC ] = { /* 812 */
+	.pme_name = "PM_LSU0_1_LRQF_FULL_CYC",
+	.pme_code = 0x000000D0BC,
+	.pme_short_desc = "Counts the number of cycles the LRQF is full.",
+	.pme_long_desc = "Counts the number of cycles the LRQF is full. LRQF is the queue that holds loads between finish and completion. If it fills up, instructions stay in LRQ until completion, potentially backing up the LRQ",
+},
+[ POWER9_PME_PM_DATA_GRP_PUMP_MPRED ] = { /* 813 */
+	.pme_name = "PM_DATA_GRP_PUMP_MPRED",
+	.pme_code = 0x000002C052,
+	.pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for a demand load",
+	.pme_long_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for a demand load",
+},
+[ POWER9_PME_PM_LSU3_ERAT_HIT ] = { /* 814 */
+	.pme_name = "PM_LSU3_ERAT_HIT",
+	.pme_code = 0x000000E890,
+	.pme_short_desc = "Primary ERAT hit.",
+	.pme_long_desc = "Primary ERAT hit. There is no secondary ERAT",
+},
+[ POWER9_PME_PM_FORCED_NOP ] = { /* 815 */
+	.pme_name = "PM_FORCED_NOP",
+	.pme_code = 0x000000509C,
+	.pme_short_desc = "Instruction was forced to execute as a nop because it was found to behave like a nop (have no effect) at decode time",
+	.pme_long_desc = "Instruction was forced to execute as a nop because it was found to behave like a nop (have no effect) at decode time",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST ] = { /* 816 */
+	.pme_name = "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST",
+	.pme_code = 0x000002D148,
+	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load",
+},
+[ POWER9_PME_PM_CMPLU_STALL_LARX ] = { /* 817 */
+	.pme_name = "PM_CMPLU_STALL_LARX",
+	.pme_code = 0x000001002A,
+	.pme_short_desc = "Finish stall because the NTF instruction was a larx waiting to be satisfied",
+	.pme_long_desc = "Finish stall because the NTF instruction was a larx waiting to be satisfied",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_RL4 ] = { /* 818 */
+	.pme_name = "PM_MRK_DPTEG_FROM_RL4",
+	.pme_code = 0x000002F14A,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a marked data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L2 ] = { /* 819 */
+	.pme_name = "PM_MRK_DATA_FROM_L2",
+	.pme_code = 0x000002C126,
+	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 due to a marked load",
+},
+[ POWER9_PME_PM_TM_FAIL_CONF_NON_TM ] = { /* 820 */
+	.pme_name = "PM_TM_FAIL_CONF_NON_TM",
+	.pme_code = 0x00000028A8,
+	.pme_short_desc = "TM aborted because a conflict occurred with a non-transactional access by another processor",
+	.pme_long_desc = "TM aborted because a conflict occurred with a non-transactional access by another processor",
+},
+[ POWER9_PME_PM_DPTEG_FROM_RL2L3_SHR ] = { /* 821 */
+	.pme_name = "PM_DPTEG_FROM_RL2L3_SHR",
+	.pme_code = 0x000001E04A,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_DARQ_4_6_ENTRIES ] = { /* 822 */
+	.pme_name = "PM_DARQ_4_6_ENTRIES",
+	.pme_code = 0x000003504E,
+	.pme_short_desc = "Cycles in which 4, 5, or 6 DARQ entries (out of 12) are in use",
+	.pme_long_desc = "Cycles in which 4, 5, or 6 DARQ entries (out of 12) are in use",
+},
+[ POWER9_PME_PM_L2_SYS_PUMP ] = { /* 823 */
+	.pme_name = "PM_L2_SYS_PUMP",
+	.pme_code = 0x000004688A,
+	.pme_short_desc = "RC requests that were system pump attempts",
+	.pme_long_desc = "RC requests that were system pump attempts",
+},
+[ POWER9_PME_PM_IOPS_CMPL ] = { /* 824 */
+	.pme_name = "PM_IOPS_CMPL",
+	.pme_code = 0x0000024050,
+	.pme_short_desc = "Internal Operations completed",
+	.pme_long_desc = "Internal Operations completed",
+},
+[ POWER9_PME_PM_LSU_FLUSH_LHS ] = { /* 825 */
+	.pme_name = "PM_LSU_FLUSH_LHS",
+	.pme_code = 0x000000C8B4,
+	.pme_short_desc = "Effective Address alias flush : no EA match but Real Address match.",
+	.pme_long_desc = "Effective Address alias flush : no EA match but Real Address match. If the data has not yet been returned for this load, the instruction will just be rejected, but if it has returned data, it will be flushed",
+},
+[ POWER9_PME_PM_DATA_FROM_L3_1_SHR ] = { /* 826 */
+	.pme_name = "PM_DATA_FROM_L3_1_SHR",
+	.pme_code = 0x000001C046,
+	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a demand load",
+},
+[ POWER9_PME_PM_NTC_FIN ] = { /* 827 */
+	.pme_name = "PM_NTC_FIN",
+	.pme_code = 0x000002405A,
+	.pme_short_desc = "Cycles in which the oldest instruction in the pipeline (NTC) finishes.",
+	.pme_long_desc = "Cycles in which the oldest instruction in the pipeline (NTC) finishes. This event is used to account for cycles in which work is being completed in the CPI stack",
+},
+[ POWER9_PME_PM_LS2_DC_COLLISIONS ] = { /* 828 */
+	.pme_name = "PM_LS2_DC_COLLISIONS",
+	.pme_code = 0x000000D094,
+	.pme_short_desc = "Read-write data cache collisions",
+	.pme_long_desc = "Read-write data cache collisions",
+},
+[ POWER9_PME_PM_FMA_CMPL ] = { /* 829 */
+	.pme_name = "PM_FMA_CMPL",
+	.pme_code = 0x0000010014,
+	.pme_short_desc = "two flops operation completed (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only.",
+	.pme_long_desc = "two flops operation completed (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only.?",
+},
+[ POWER9_PME_PM_IPTEG_FROM_MEMORY ] = { /* 830 */
+	.pme_name = "PM_IPTEG_FROM_MEMORY",
+	.pme_code = 0x000002504C,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request",
+},
+[ POWER9_PME_PM_TM_NON_FAV_TBEGIN ] = { /* 831 */
+	.pme_name = "PM_TM_NON_FAV_TBEGIN",
+	.pme_code = 0x000000289C,
+	.pme_short_desc = "Dispatch time non favored tbegin",
+	.pme_long_desc = "Dispatch time non favored tbegin",
+},
+[ POWER9_PME_PM_PMC1_REWIND ] = { /* 832 */
+	.pme_name = "PM_PMC1_REWIND",
+	.pme_code = 0x000004D02C,
+	.pme_short_desc = "",
+	.pme_long_desc = "",
+},
+[ POWER9_PME_PM_ISU2_ISS_HOLD_ALL ] = { /* 833 */
+	.pme_name = "PM_ISU2_ISS_HOLD_ALL",
+	.pme_code = 0x0000003880,
+	.pme_short_desc = "All ISU rejects",
+	.pme_long_desc = "All ISU rejects",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_DL2L3_MOD_CYC ] = { /* 834 */
+	.pme_name = "PM_MRK_DATA_FROM_DL2L3_MOD_CYC",
+	.pme_code = 0x000004D12E,
+	.pme_short_desc = "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
+},
+[ POWER9_PME_PM_PTESYNC ] = { /* 835 */
+	.pme_name = "PM_PTESYNC",
+	.pme_code = 0x000000589C,
+	.pme_short_desc = "ptesync instruction counted when the instructio is decoded and transmitted",
+	.pme_long_desc = "ptesync instruction counted when the instructio is decoded and transmitted",
+},
+[ POWER9_PME_PM_ISIDE_DISP_FAIL_OTHER ] = { /* 836 */
+	.pme_name = "PM_ISIDE_DISP_FAIL_OTHER",
+	.pme_code = 0x000002688A,
+	.pme_short_desc = "All i-side dispatch attempts that failed due to a reason other than addrs collision",
+	.pme_long_desc = "All i-side dispatch attempts that failed due to a reason other than addrs collision",
+},
+[ POWER9_PME_PM_L2_IC_INV ] = { /* 837 */
+	.pme_name = "PM_L2_IC_INV",
+	.pme_code = 0x0000026082,
+	.pme_short_desc = "Icache Invalidates from L2",
+	.pme_long_desc = "Icache Invalidates from L2",
+},
+[ POWER9_PME_PM_DPTEG_FROM_L3 ] = { /* 838 */
+	.pme_name = "PM_DPTEG_FROM_L3",
+	.pme_code = 0x000004E042,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_RADIX_PWC_L2_HIT ] = { /* 839 */
+	.pme_name = "PM_RADIX_PWC_L2_HIT",
+	.pme_code = 0x000002D024,
+	.pme_short_desc = "A radix translation attempt missed in the TLB but hit on both the first and second levels of page walk cache.",
+	.pme_long_desc = "A radix translation attempt missed in the TLB but hit on both the first and second levels of page walk cache.",
+},
+[ POWER9_PME_PM_DC_PREF_HW_ALLOC ] = { /* 840 */
+	.pme_name = "PM_DC_PREF_HW_ALLOC",
+	.pme_code = 0x000000F0A4,
+	.pme_short_desc = "Prefetch stream allocated by the hardware prefetch mechanism",
+	.pme_long_desc = "Prefetch stream allocated by the hardware prefetch mechanism",
+},
+[ POWER9_PME_PM_LSU0_VECTOR_LD_FIN ] = { /* 841 */
+	.pme_name = "PM_LSU0_VECTOR_LD_FIN",
+	.pme_code = 0x000000C080,
+	.pme_short_desc = "A vector load instruction finished.",
+	.pme_long_desc = "A vector load instruction finished. The ops considered in this category are lxv*, lvx*, lve*, lxsi*zx, lxvwsx, lxsd, lxssp, lxvl, lxvll, lxvb16x, lxvh8x, lxv, lxvx",
+},
+[ POWER9_PME_PM_1PLUS_PPC_DISP ] = { /* 842 */
+	.pme_name = "PM_1PLUS_PPC_DISP",
+	.pme_code = 0x00000400F2,
+	.pme_short_desc = "Cycles at least one Instr Dispatched",
+	.pme_long_desc = "Cycles at least one Instr Dispatched",
+},
+[ POWER9_PME_PM_RADIX_PWC_L3_PTE_FROM_L2 ] = { /* 843 */
+	.pme_name = "PM_RADIX_PWC_L3_PTE_FROM_L2",
+	.pme_code = 0x000002D02E,
+	.pme_short_desc = "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 data cache.",
+	.pme_long_desc = "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 data cache. This implies that a level 4 PWC access was not necessary for this translation",
+},
+[ POWER9_PME_PM_DATA_FROM_L2MISS ] = { /* 844 */
+	.pme_name = "PM_DATA_FROM_L2MISS",
+	.pme_code = 0x00000200FE,
+	.pme_short_desc = "Demand LD - L2 Miss (not L2 hit)",
+	.pme_long_desc = "Demand LD - L2 Miss (not L2 hit)",
+},
+[ POWER9_PME_PM_MRK_FAB_RSP_RD_T_INTV ] = { /* 845 */
+	.pme_name = "PM_MRK_FAB_RSP_RD_T_INTV",
+	.pme_code = 0x000001015E,
+	.pme_short_desc = "Sampled Read got a T intervention",
+	.pme_long_desc = "Sampled Read got a T intervention",
+},
+[ POWER9_PME_PM_NTC_ISSUE_HELD_ARB ] = { /* 846 */
+	.pme_name = "PM_NTC_ISSUE_HELD_ARB",
+	.pme_code = 0x000002E016,
+	.pme_short_desc = "The NTC instruction is being held at dispatch because it lost arbitration onto the issue pipe to another instruction (from the same thread or a different thread)",
+	.pme_long_desc = "The NTC instruction is being held at dispatch because it lost arbitration onto the issue pipe to another instruction (from the same thread or a different thread)",
+},
+[ POWER9_PME_PM_LSU2_L1_CAM_CANCEL ] = { /* 847 */
+	.pme_name = "PM_LSU2_L1_CAM_CANCEL",
+	.pme_code = 0x000000F094,
+	.pme_short_desc = "ls2 l1 tm cam cancel",
+	.pme_long_desc = "ls2 l1 tm cam cancel",
+},
+[ POWER9_PME_PM_L3_GRP_GUESS_WRONG_HIGH ] = { /* 848 */
+	.pme_name = "PM_L3_GRP_GUESS_WRONG_HIGH",
+	.pme_code = 0x00000368B2,
+	.pme_short_desc = "Initial scope=group but data from local node.",
+	.pme_long_desc = "Initial scope=group but data from local node. Predition too high",
+},
+[ POWER9_PME_PM_DATA_FROM_L3_NO_CONFLICT ] = { /* 849 */
+	.pme_name = "PM_DATA_FROM_L3_NO_CONFLICT",
+	.pme_code = 0x000001C044,
+	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load",
+},
+[ POWER9_PME_PM_SUSPENDED ] = { /* 850 */
+	.pme_name = "PM_SUSPENDED",
+	.pme_code = 0x0000010000,
+	.pme_short_desc = "Counter OFF",
+	.pme_long_desc = "Counter OFF",
+},
+[ POWER9_PME_PM_L3_SYS_GUESS_WRONG ] = { /* 851 */
+	.pme_name = "PM_L3_SYS_GUESS_WRONG",
+	.pme_code = 0x00000460B2,
+	.pme_short_desc = "Initial scope=system but data from local or near.",
+	.pme_long_desc = "Initial scope=system but data from local or near. Predction too high",
+},
+[ POWER9_PME_PM_L3_L2_CO_HIT ] = { /* 852 */
+	.pme_name = "PM_L3_L2_CO_HIT",
+	.pme_code = 0x00000360A2,
+	.pme_short_desc = "L2 castout hits",
+	.pme_long_desc = "L2 castout hits",
+},
+[ POWER9_PME_PM_LSU0_TM_L1_HIT ] = { /* 853 */
+	.pme_name = "PM_LSU0_TM_L1_HIT",
+	.pme_code = 0x000000E094,
+	.pme_short_desc = "Load tm hit in L1",
+	.pme_long_desc = "Load tm hit in L1",
+},
+[ POWER9_PME_PM_BR_MPRED_PCACHE ] = { /* 854 */
+	.pme_name = "PM_BR_MPRED_PCACHE",
+	.pme_code = 0x00000048B0,
+	.pme_short_desc = "Conditional Branch Completed that was Mispredicted due to pattern cache prediction",
+	.pme_long_desc = "Conditional Branch Completed that was Mispredicted due to pattern cache prediction",
+},
+[ POWER9_PME_PM_STCX_FAIL ] = { /* 855 */
+	.pme_name = "PM_STCX_FAIL",
+	.pme_code = 0x000001E058,
+	.pme_short_desc = "stcx failed",
+	.pme_long_desc = "stcx failed",
+},
+[ POWER9_PME_PM_LSU_FLUSH_NEXT ] = { /* 856 */
+	.pme_name = "PM_LSU_FLUSH_NEXT",
+	.pme_code = 0x00000020B0,
+	.pme_short_desc = "LSU flush next reported at flush time.",
+	.pme_long_desc = "LSU flush next reported at flush time. Sometimes these also come with an exception",
+},
+[ POWER9_PME_PM_DSIDE_MRU_TOUCH ] = { /* 857 */
+	.pme_name = "PM_DSIDE_MRU_TOUCH",
+	.pme_code = 0x0000026884,
+	.pme_short_desc = "dside L2 MRU touch",
+	.pme_long_desc = "dside L2 MRU touch",
+},
+[ POWER9_PME_PM_SN_MISS ] = { /* 858 */
+	.pme_name = "PM_SN_MISS",
+	.pme_code = 0x00000468A8,
+	.pme_short_desc = "Any port snooper miss.",
+	.pme_long_desc = "Any port snooper miss. Up to 4 can happen in a cycle but we only count 1",
+},
+[ POWER9_PME_PM_BR_PRED_TAKEN_CMPL ] = { /* 859 */
+	.pme_name = "PM_BR_PRED_TAKEN_CMPL",
+	.pme_code = 0x000000489C,
+	.pme_short_desc = "Conditional Branch Completed in which the HW predicted the Direction or Target and the branch was resolved taken.",
+	.pme_long_desc = "Conditional Branch Completed in which the HW predicted the Direction or Target and the branch was resolved taken. Counted at completion time",
+},
+[ POWER9_PME_PM_L3_P0_SYS_PUMP ] = { /* 860 */
+	.pme_name = "PM_L3_P0_SYS_PUMP",
+	.pme_code = 0x00000360B0,
+	.pme_short_desc = "L3 pf sent with sys scope port 0",
+	.pme_long_desc = "L3 pf sent with sys scope port 0",
+},
+[ POWER9_PME_PM_L3_HIT ] = { /* 861 */
+	.pme_name = "PM_L3_HIT",
+	.pme_code = 0x00000160A4,
+	.pme_short_desc = "L3 Hits",
+	.pme_long_desc = "L3 Hits",
+},
+[ POWER9_PME_PM_MRK_DFU_FIN ] = { /* 862 */
+	.pme_name = "PM_MRK_DFU_FIN",
+	.pme_code = 0x0000020132,
+	.pme_short_desc = "Decimal Unit marked Instruction Finish",
+	.pme_long_desc = "Decimal Unit marked Instruction Finish",
+},
+[ POWER9_PME_PM_CMPLU_STALL_NESTED_TEND ] = { /* 863 */
+	.pme_name = "PM_CMPLU_STALL_NESTED_TEND",
+	.pme_code = 0x000003003C,
+	.pme_short_desc = "Completion stall because the ISU is updating the TEXASR to keep track of the nested tend and decrement the TEXASR nested level.",
+	.pme_long_desc = "Completion stall because the ISU is updating the TEXASR to keep track of the nested tend and decrement the TEXASR nested level. This is a short delay",
+},
+[ POWER9_PME_PM_INST_FROM_L1 ] = { /* 864 */
+	.pme_name = "PM_INST_FROM_L1",
+	.pme_code = 0x0000004080,
+	.pme_short_desc = "Instruction fetches from L1.",
+	.pme_long_desc = "Instruction fetches from L1. L1 instruction hit",
+},
+[ POWER9_PME_PM_IC_DEMAND_REQ ] = { /* 865 */
+	.pme_name = "PM_IC_DEMAND_REQ",
+	.pme_code = 0x0000004088,
+	.pme_short_desc = "Demand Instruction fetch request",
+	.pme_long_desc = "Demand Instruction fetch request",
+},
+[ POWER9_PME_PM_BRU_FIN ] = { /* 866 */
+	.pme_name = "PM_BRU_FIN",
+	.pme_code = 0x0000010068,
+	.pme_short_desc = "Branch Instruction Finished",
+	.pme_long_desc = "Branch Instruction Finished",
+},
+[ POWER9_PME_PM_L1_ICACHE_RELOADED_ALL ] = { /* 867 */
+	.pme_name = "PM_L1_ICACHE_RELOADED_ALL",
+	.pme_code = 0x0000040012,
+	.pme_short_desc = "Counts all Icache reloads includes demand, prefetch, prefetch turned into demand and demand turned into prefetch",
+	.pme_long_desc = "Counts all Icache reloads includes demand, prefetch, prefetch turned into demand and demand turned into prefetch",
+},
+[ POWER9_PME_PM_IERAT_RELOAD_16M ] = { /* 868 */
+	.pme_name = "PM_IERAT_RELOAD_16M",
+	.pme_code = 0x000004006A,
+	.pme_short_desc = "IERAT Reloaded (Miss) for a 16M page",
+	.pme_long_desc = "IERAT Reloaded (Miss) for a 16M page",
+},
+[ POWER9_PME_PM_DATA_FROM_L2MISS_MOD ] = { /* 869 */
+	.pme_name = "PM_DATA_FROM_L2MISS_MOD",
+	.pme_code = 0x000001C04E,
+	.pme_short_desc = "The processor's data cache was reloaded from a localtion other than the local core's L2 due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded from a localtion other than the local core's L2 due to a demand load",
+},
+[ POWER9_PME_PM_LSU0_ERAT_HIT ] = { /* 870 */
+	.pme_name = "PM_LSU0_ERAT_HIT",
+	.pme_code = 0x000000E08C,
+	.pme_short_desc = "Primary ERAT hit.",
+	.pme_long_desc = "Primary ERAT hit. There is no secondary ERAT",
+},
+[ POWER9_PME_PM_L3_PF0_BUSY ] = { /* 871 */
+	.pme_name = "PM_L3_PF0_BUSY",
+	.pme_code = 0x00000460B4,
+	.pme_short_desc = "lifetime, sample of PF machine 0 valid",
+	.pme_long_desc = "lifetime, sample of PF machine 0 valid",
+},
+[ POWER9_PME_PM_MRK_DPTEG_FROM_LL4 ] = { /* 872 */
+	.pme_name = "PM_MRK_DPTEG_FROM_LL4",
+	.pme_code = 0x000001F14C,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_LSU3_SET_MPRED ] = { /* 873 */
+	.pme_name = "PM_LSU3_SET_MPRED",
+	.pme_code = 0x000000D884,
+	.pme_short_desc = "Set prediction(set-p) miss.",
+	.pme_long_desc = "Set prediction(set-p) miss. The entry was not found in the Set prediction table",
+},
+[ POWER9_PME_PM_TM_CAM_OVERFLOW ] = { /* 874 */
+	.pme_name = "PM_TM_CAM_OVERFLOW",
+	.pme_code = 0x00000168A6,
+	.pme_short_desc = "l3 tm cam overflow during L2 co of SC",
+	.pme_long_desc = "l3 tm cam overflow during L2 co of SC",
+},
+[ POWER9_PME_PM_SYNC_MRK_FX_DIVIDE ] = { /* 875 */
+	.pme_name = "PM_SYNC_MRK_FX_DIVIDE",
+	.pme_code = 0x0000015156,
+	.pme_short_desc = "Marked fixed point divide that can cause a synchronous interrupt",
+	.pme_long_desc = "Marked fixed point divide that can cause a synchronous interrupt",
+},
+[ POWER9_PME_PM_IPTEG_FROM_L2_1_SHR ] = { /* 876 */
+	.pme_name = "PM_IPTEG_FROM_L2_1_SHR",
+	.pme_code = 0x0000035046,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a instruction side request",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a instruction side request",
+},
+[ POWER9_PME_PM_MRK_LD_MISS_L1 ] = { /* 877 */
+	.pme_name = "PM_MRK_LD_MISS_L1",
+	.pme_code = 0x00000201E2,
+	.pme_short_desc = "Marked DL1 Demand Miss counted at exec time.",
+	.pme_long_desc = "Marked DL1 Demand Miss counted at exec time. Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load.",
+},
+[ POWER9_PME_PM_MRK_FAB_RSP_DCLAIM ] = { /* 878 */
+	.pme_name = "PM_MRK_FAB_RSP_DCLAIM",
+	.pme_code = 0x0000030154,
+	.pme_short_desc = "Marked store had to do a dclaim",
+	.pme_long_desc = "Marked store had to do a dclaim",
+},
+[ POWER9_PME_PM_IPTEG_FROM_L3_DISP_CONFLICT ] = { /* 879 */
+	.pme_name = "PM_IPTEG_FROM_L3_DISP_CONFLICT",
+	.pme_code = 0x0000035042,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a instruction side request",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a instruction side request",
+},
+[ POWER9_PME_PM_NON_FMA_FLOP_CMPL ] = { /* 880 */
+	.pme_name = "PM_NON_FMA_FLOP_CMPL",
+	.pme_code = 0x000004D056,
+	.pme_short_desc = "Non fma flop instruction completed",
+	.pme_long_desc = "Non fma flop instruction completed",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L2MISS ] = { /* 881 */
+	.pme_name = "PM_MRK_DATA_FROM_L2MISS",
+	.pme_code = 0x00000401E8,
+	.pme_short_desc = "The processor's data cache was reloaded from a localtion other than the local core's L2 due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded from a localtion other than the local core's L2 due to a marked load",
+},
+[ POWER9_PME_PM_L2_SYS_GUESS_WRONG ] = { /* 882 */
+	.pme_name = "PM_L2_SYS_GUESS_WRONG",
+	.pme_code = 0x0000036888,
+	.pme_short_desc = "L2 guess sys and guess was not correct (ie data ^beyond-6chip)",
+	.pme_long_desc = "L2 guess sys and guess was not correct (ie data ^beyond-6chip)",
+},
+[ POWER9_PME_PM_THRESH_EXC_2048 ] = { /* 883 */
+	.pme_name = "PM_THRESH_EXC_2048",
+	.pme_code = 0x00000401EC,
+	.pme_short_desc = "Threshold counter exceeded a value of 2048",
+	.pme_long_desc = "Threshold counter exceeded a value of 2048",
+},
+[ POWER9_PME_PM_INST_FROM_LL4 ] = { /* 884 */
+	.pme_name = "PM_INST_FROM_LL4",
+	.pme_code = 0x000001404C,
+	.pme_short_desc = "The processor's Instruction cache was reloaded from the local chip's L4 cache due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded from the local chip's L4 cache due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_DATA_FROM_RL2L3_SHR ] = { /* 885 */
+	.pme_name = "PM_DATA_FROM_RL2L3_SHR",
+	.pme_code = 0x000001C04A,
+	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load",
+},
+[ POWER9_PME_PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST ] = { /* 886 */
+	.pme_name = "PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST",
+	.pme_code = 0x000003C040,
+	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load",
+	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load",
+},
+[ POWER9_PME_PM_LSU_FLUSH_WRK_ARND ] = { /* 887 */
+	.pme_name = "PM_LSU_FLUSH_WRK_ARND",
+	.pme_code = 0x000000C0B4,
+	.pme_short_desc = "LSU workaround flush.",
+	.pme_long_desc = "LSU workaround flush. These flushes are setup with programmable scan only latches to perform various actions when the flsh macro receives a trigger from the dbg macros. These actions include things like flushing the next op encountered for a particular thread or flushing the next op that is NTC op that is encountered on a particular slice. The kind of flush that the workaround is setup to perform is highly variable.",
+},
+[ POWER9_PME_PM_L3_PF_HIT_L3 ] = { /* 888 */
+	.pme_name = "PM_L3_PF_HIT_L3",
+	.pme_code = 0x00000260A8,
+	.pme_short_desc = "l3 pf hit in l3",
+	.pme_long_desc = "l3 pf hit in l3",
+},
+[ POWER9_PME_PM_RD_FORMING_SC ] = { /* 889 */
+	.pme_name = "PM_RD_FORMING_SC",
+	.pme_code = 0x00000460A6,
+	.pme_short_desc = "rd forming sc",
+	.pme_long_desc = "rd forming sc",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_L2_1_MOD_CYC ] = { /* 890 */
+	.pme_name = "PM_MRK_DATA_FROM_L2_1_MOD_CYC",
+	.pme_code = 0x000003D148,
+	.pme_short_desc = "Duration in cycles to reload with Modified (M) data from another core's L2 on the same chip due to a marked load",
+	.pme_long_desc = "Duration in cycles to reload with Modified (M) data from another core's L2 on the same chip due to a marked load",
+},
+[ POWER9_PME_PM_IPTEG_FROM_DL4 ] = { /* 891 */
+	.pme_name = "PM_IPTEG_FROM_DL4",
+	.pme_code = 0x000003504C,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a instruction side request",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a instruction side request",
+},
+[ POWER9_PME_PM_CMPLU_STALL_STORE_FINISH ] = { /* 892 */
+	.pme_name = "PM_CMPLU_STALL_STORE_FINISH",
+	.pme_code = 0x000002C014,
+	.pme_short_desc = "Finish stall because the NTF instruction was a store with all its dependencies met, just waiting to go through the LSU pipe to finish",
+	.pme_long_desc = "Finish stall because the NTF instruction was a store with all its dependencies met, just waiting to go through the LSU pipe to finish",
+},
+[ POWER9_PME_PM_IPTEG_FROM_LL4 ] = { /* 893 */
+	.pme_name = "PM_IPTEG_FROM_LL4",
+	.pme_code = 0x000001504C,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side request",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side request",
+},
+[ POWER9_PME_PM_1FLOP_CMPL ] = { /* 894 */
+	.pme_name = "PM_1FLOP_CMPL",
+	.pme_code = 0x000001000C,
+	.pme_short_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation completed",
+	.pme_long_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation completed",
+},
+[ POWER9_PME_PM_L2_GRP_GUESS_WRONG ] = { /* 895 */
+	.pme_name = "PM_L2_GRP_GUESS_WRONG",
+	.pme_code = 0x0000026888,
+	.pme_short_desc = "L2 guess grp and guess was not correct (ie data on-chip OR beyond-6chip)",
+	.pme_long_desc = "L2 guess grp and guess was not correct (ie data on-chip OR beyond-6chip)",
+},
+[ POWER9_PME_PM_TM_FAV_TBEGIN ] = { /* 896 */
+	.pme_name = "PM_TM_FAV_TBEGIN",
+	.pme_code = 0x000000209C,
+	.pme_short_desc = "Dispatch time Favored tbegin",
+	.pme_long_desc = "Dispatch time Favored tbegin",
+},
+[ POWER9_PME_PM_INST_FROM_L2_NO_CONFLICT ] = { /* 897 */
+	.pme_name = "PM_INST_FROM_L2_NO_CONFLICT",
+	.pme_code = 0x0000014040,
+	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 without conflict due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 without conflict due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_2FLOP_CMPL ] = { /* 898 */
+	.pme_name = "PM_2FLOP_CMPL",
+	.pme_code = 0x000004D052,
+	.pme_short_desc = "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg?",
+	.pme_long_desc = "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg?",
+},
+[ POWER9_PME_PM_LS2_TM_DISALLOW ] = { /* 899 */
+	.pme_name = "PM_LS2_TM_DISALLOW",
+	.pme_code = 0x000000E0B8,
+	.pme_short_desc = "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it",
+	.pme_long_desc = "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it",
+},
+[ POWER9_PME_PM_L2_LD_DISP ] = { /* 900 */
+	.pme_name = "PM_L2_LD_DISP",
+	.pme_code = 0x000001609E,
+	.pme_short_desc = "All successful load dispatches",
+	.pme_long_desc = "All successful load dispatches",
+},
+[ POWER9_PME_PM_CMPLU_STALL_LHS ] = { /* 901 */
+	.pme_name = "PM_CMPLU_STALL_LHS",
+	.pme_code = 0x000002C01A,
+	.pme_short_desc = "Finish stall because the NTF instruction was a load that hit on an older store and it was waiting for store data",
+	.pme_long_desc = "Finish stall because the NTF instruction was a load that hit on an older store and it was waiting for store data",
+},
+[ POWER9_PME_PM_TLB_HIT ] = { /* 902 */
+	.pme_name = "PM_TLB_HIT",
+	.pme_code = 0x000001F054,
+	.pme_short_desc = "Number of times the TLB had the data required by the instruction.",
+	.pme_long_desc = "Number of times the TLB had the data required by the instruction. Applies to both HPT and RPT",
+},
+[ POWER9_PME_PM_HV_CYC ] = { /* 903 */
+	.pme_name = "PM_HV_CYC",
+	.pme_code = 0x0000020006,
+	.pme_short_desc = "Cycles in which msr_hv is high.",
+	.pme_long_desc = "Cycles in which msr_hv is high. Note that this event does not take msr_pr into consideration",
+},
+[ POWER9_PME_PM_L2_RTY_LD ] = { /* 904 */
+	.pme_name = "PM_L2_RTY_LD",
+	.pme_code = 0x000003689E,
+	.pme_short_desc = "RC retries on PB for any load from core",
+	.pme_long_desc = "RC retries on PB for any load from core",
+},
+[ POWER9_PME_PM_STCX_SUCCESS_CMPL ] = { /* 905 */
+	.pme_name = "PM_STCX_SUCCESS_CMPL",
+	.pme_code = 0x000000C8BC,
+	.pme_short_desc = "Number of stcx instructions that completed successfully",
+	.pme_long_desc = "Number of stcx instructions that completed successfully",
+},
+[ POWER9_PME_PM_INST_PUMP_MPRED ] = { /* 906 */
+	.pme_name = "PM_INST_PUMP_MPRED",
+	.pme_code = 0x0000044052,
+	.pme_short_desc = "Pump misprediction.",
+	.pme_long_desc = "Pump misprediction. Counts across all types of pumps for an instruction fetch",
+},
+[ POWER9_PME_PM_LSU2_ERAT_HIT ] = { /* 907 */
+	.pme_name = "PM_LSU2_ERAT_HIT",
+	.pme_code = 0x000000E090,
+	.pme_short_desc = "Primary ERAT hit.",
+	.pme_long_desc = "Primary ERAT hit. There is no secondary ERAT",
+},
+[ POWER9_PME_PM_INST_FROM_RL4 ] = { /* 908 */
+	.pme_name = "PM_INST_FROM_RL4",
+	.pme_code = 0x000002404A,
+	.pme_short_desc = "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)",
+	.pme_long_desc = "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)",
+},
+[ POWER9_PME_PM_LD_L3MISS_PEND_CYC ] = { /* 909 */
+	.pme_name = "PM_LD_L3MISS_PEND_CYC",
+	.pme_code = 0x0000010062,
+	.pme_short_desc = "Cycles L3 miss was pending for this thread",
+	.pme_long_desc = "Cycles L3 miss was pending for this thread",
+},
+[ POWER9_PME_PM_L3_LAT_CI_MISS ] = { /* 910 */
+	.pme_name = "PM_L3_LAT_CI_MISS",
+	.pme_code = 0x00000468A2,
+	.pme_short_desc = "L3 Lateral Castins Miss",
+	.pme_long_desc = "L3 Lateral Castins Miss",
+},
+[ POWER9_PME_PM_MRK_FAB_RSP_RD_RTY ] = { /* 911 */
+	.pme_name = "PM_MRK_FAB_RSP_RD_RTY",
+	.pme_code = 0x000004015E,
+	.pme_short_desc = "Sampled L2 reads retry count",
+	.pme_long_desc = "Sampled L2 reads retry count",
+},
+[ POWER9_PME_PM_DTLB_MISS_16M ] = { /* 912 */
+	.pme_name = "PM_DTLB_MISS_16M",
+	.pme_code = 0x000004C056,
+	.pme_short_desc = "Data TLB Miss page size 16M",
+	.pme_long_desc = "Data TLB Miss page size 16M",
+},
+[ POWER9_PME_PM_DPTEG_FROM_L2_1_MOD ] = { /* 913 */
+	.pme_name = "PM_DPTEG_FROM_L2_1_MOD",
+	.pme_code = 0x000004E046,
+	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a data side request.",
+	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
+},
+[ POWER9_PME_PM_MRK_DATA_FROM_RL2L3_SHR ] = { /* 914 */
+	.pme_name = "PM_MRK_DATA_FROM_RL2L3_SHR",
+	.pme_code = 0x0000035150,
+	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
+	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
+},
+[ POWER9_PME_PM_MRK_LSU_FIN ] = { /* 915 */
+	.pme_name = "PM_MRK_LSU_FIN",
+	.pme_code = 0x0000040132,
+	.pme_short_desc = "lsu marked instr PPC finish",
+	.pme_long_desc = "lsu marked instr PPC finish",
+},
+[ POWER9_PME_PM_LSU0_STORE_REJECT ] = { /* 916 */
+	.pme_name = "PM_LSU0_STORE_REJECT",
+	.pme_code = 0x000000F08C,
+	.pme_short_desc = "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met",
+	.pme_long_desc = "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met",
+},
+[ POWER9_PME_PM_CLB_HELD ] = { /* 917 */
+	.pme_name = "PM_CLB_HELD",
+	.pme_code = 0x000000208C,
+	.pme_short_desc = "CLB Hold: Any Reason",
+	.pme_long_desc = "CLB Hold: Any Reason",
+},
+[ POWER9_PME_PM_LS2_ERAT_MISS_PREF ] = { /* 918 */
+	.pme_name = "PM_LS2_ERAT_MISS_PREF",
+	.pme_code = 0x000000E088,
+	.pme_short_desc = "LS0 Erat miss due to prefetch",
+	.pme_long_desc = "LS0 Erat miss due to prefetch",
+},
+};
+#endif
diff --git a/lib/pfmlib_common.c b/lib/pfmlib_common.c
index 6ff4499..bd57078 100644
--- a/lib/pfmlib_common.c
+++ b/lib/pfmlib_common.c
@@ -286,6 +286,7 @@ static pfmlib_pmu_t *pfmlib_pmus[]=
 	&power6_support,
 	&power7_support,
 	&power8_support,
+	&power9_support,
 	&torrent_support,
     &powerpc_nest_mcs_read_support,
     &powerpc_nest_mcs_write_support,
diff --git a/lib/pfmlib_power9.c b/lib/pfmlib_power9.c
new file mode 100644
index 0000000..b3807da
--- /dev/null
+++ b/lib/pfmlib_power9.c
@@ -0,0 +1,58 @@
+/*
+ * pfmlib_power9.c : IBM Power9 support
+ *
+ * Copyright (C) IBM Corporation, 2017.  All rights reserved.
+ * Contributed by Will Schmidt (will_schmidt@vnet.ibm.com)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
+ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+/* private headers */
+#include "pfmlib_priv.h"
+#include "pfmlib_power_priv.h"
+#include "events/power9_events.h"
+
+static int
+pfm_power9_detect(void* this)
+{
+	if (__is_processor(PV_POWER9))
+		return PFM_SUCCESS;
+	return PFM_ERR_NOTSUPP;
+}
+
+pfmlib_pmu_t power9_support={
+	.desc			= "POWER9",
+	.name			= "power9",
+	.pmu			= PFM_PMU_POWER9,
+	.pme_count		= LIBPFM_ARRAY_SIZE(power9_pe),
+	.type			= PFM_PMU_TYPE_CORE,
+	.supported_plm		= POWER9_PLM,
+	.num_cntrs		= 4,
+	.num_fixed_cntrs	= 2,
+	.max_encoding		= 1,
+	.pe			= power9_pe,
+	.pmu_detect		= pfm_power9_detect,
+	.get_event_encoding[PFM_OS_NONE] = pfm_gen_powerpc_get_encoding,
+	 PFMLIB_ENCODE_PERF(pfm_gen_powerpc_get_perf_encoding),
+	 PFMLIB_VALID_PERF_PATTRS(pfm_gen_powerpc_perf_validate_pattrs),
+	.get_event_first	= pfm_gen_powerpc_get_event_first,
+	.get_event_next		= pfm_gen_powerpc_get_event_next,
+	.event_is_valid		= pfm_gen_powerpc_event_is_valid,
+	.validate_table		= pfm_gen_powerpc_validate_table,
+	.get_event_info		= pfm_gen_powerpc_get_event_info,
+	.get_event_attr_info	= pfm_gen_powerpc_get_event_attr_info,
+};
diff --git a/lib/pfmlib_power_priv.h b/lib/pfmlib_power_priv.h
index 3b72d32..6fce092 100644
--- a/lib/pfmlib_power_priv.h
+++ b/lib/pfmlib_power_priv.h
@@ -96,9 +96,11 @@ typedef struct {
 #define PV_POWER8E	0x004b
 #define PV_POWER8NVL	0x004c
 #define PV_POWER8	0x004d
+#define PV_POWER9	0x004e
 
 #define POWER_PLM (PFM_PLM0|PFM_PLM3)
 #define POWER8_PLM (POWER_PLM|PFM_PLMH)
+#define POWER9_PLM (POWER_PLM|PFM_PLMH)
 
 extern int pfm_gen_powerpc_get_event_info(void *this, int pidx, pfm_event_info_t *info);
 extern int pfm_gen_powerpc_get_event_attr_info(void *this, int pidx, int umask_idx, pfm_event_attr_info_t *info);
diff --git a/lib/pfmlib_priv.h b/lib/pfmlib_priv.h
index b7503a7..1f80571 100644
--- a/lib/pfmlib_priv.h
+++ b/lib/pfmlib_priv.h
@@ -448,6 +448,7 @@ extern pfmlib_pmu_t power5p_support;
 extern pfmlib_pmu_t power6_support;
 extern pfmlib_pmu_t power7_support;
 extern pfmlib_pmu_t power8_support;
+extern pfmlib_pmu_t power9_support;
 extern pfmlib_pmu_t torrent_support;
 extern pfmlib_pmu_t powerpc_nest_mcs_read_support;
 extern pfmlib_pmu_t powerpc_nest_mcs_write_support;

Places

File libpfm_enable-ibm-power9-core-pmu-support-beta.patch of Package libpfm (Revision 4bc59235482d9c14451d644efdd161fd)

Places