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openSUSE:Leap:15.0:Rings:1-MinimalX
xen
5aaa9878-x86-vlapic-clear-TMR-bit-for-edge-trig...
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File 5aaa9878-x86-vlapic-clear-TMR-bit-for-edge-triggered-intr.patch of Package xen
# Commit 12a50030a81a14a3c7be672ddfde707b961479ec # Date 2018-03-15 16:59:52 +0100 # Author Liran Alon <liran.alon@oracle.com> # Committer Jan Beulich <jbeulich@suse.com> x86/vlapic: clear TMR bit upon acceptance of edge-triggered interrupt to IRR According to Intel SDM section "Interrupt Acceptance for Fixed Interrupts": "The trigger mode register (TMR) indicates the trigger mode of the interrupt (see Figure 10-20). Upon acceptance of an interrupt into the IRR, the corresponding TMR bit is cleared for edge-triggered interrupts and set for level-triggered interrupts. If a TMR bit is set when an EOI cycle for its corresponding interrupt vector is generated, an EOI message is sent to all I/O APICs." Before this patch TMR-bit was cleared on LAPIC EOI which is not what real hardware does. This was also confirmed in KVM upstream commit a0c9a822bf37 ("KVM: dont clear TMR on EOI"). Behavior after this patch is aligned with both Intel SDM and KVM implementation. Signed-off-by: Liran Alon <liran.alon@oracle.com> Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Reviewed-by: Jan Beulich <jbeulich@suse.com> --- a/xen/arch/x86/hvm/vlapic.c +++ b/xen/arch/x86/hvm/vlapic.c @@ -161,6 +161,8 @@ void vlapic_set_irq(struct vlapic *vlapi if ( trig ) vlapic_set_vector(vec, &vlapic->regs->data[APIC_TMR]); + else + vlapic_clear_vector(vec, &vlapic->regs->data[APIC_TMR]); if ( hvm_funcs.update_eoi_exit_bitmap ) hvm_funcs.update_eoi_exit_bitmap(target, vec, trig); @@ -434,7 +436,7 @@ void vlapic_handle_EOI(struct vlapic *vl { struct domain *d = vlapic_domain(vlapic); - if ( vlapic_test_and_clear_vector(vector, &vlapic->regs->data[APIC_TMR]) ) + if ( vlapic_test_vector(vector, &vlapic->regs->data[APIC_TMR]) ) vioapic_update_EOI(d, vector); hvm_dpci_msi_eoi(d, vector);
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