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openSUSE:Leap:15.4:ARM
perf.12679
perf-vendor-events-arm64-Enable-JSON-events-for...
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File perf-vendor-events-arm64-Enable-JSON-events-for-eMAG.patch of Package perf.12679
From b44d16b7e2a695df4973cf2a946167f256214b38 Mon Sep 17 00:00:00 2001 From: Sean V Kelley <seanvk.dev@oregontracks.org> Date: Thu, 2 Aug 2018 21:18:11 -0700 Subject: [PATCH 128/132] perf vendor events arm64: Enable JSON events for eMAG Git-commit: 704089e77acf74b17ed294683660937000ecb9ee Patch-mainline: v4.19-rc1 References: fate#325865,fate#325861 This patch adds the Ampere Computing eMAG file. This platform follows the ARMv8 recommended IMPLEMENTATION DEFINED events, where applicable. Signed-off-by: Sean V Kelley <seanvk.dev@oregontracks.org> Reviewed-by: John Garry <john.garry@huawei.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will.deacon@arm.com> Cc: William Cohen <wcohen@redhat.com> Cc: linux-arm-kernel@lists.infradead.org LPU-Reference: 20180803041811.17065-1-seanvk.dev@oregontracks.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com> Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com> --- .../arch/arm64/ampere/emag/core-imp-def.json | 32 ++++++++++++++++++++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 2 files changed, 33 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json new file mode 100644 index 00000000..bc03c06c --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json @@ -0,0 +1,32 @@ +[ + { + "ArchStdEvent": "L1D_CACHE_RD", + }, + { + "ArchStdEvent": "L1D_CACHE_WR", + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_RD", + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_WR", + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_RD", + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_WR", + }, + { + "ArchStdEvent": "L1D_TLB_RD", + }, + { + "ArchStdEvent": "L1D_TLB_WR", + }, + { + "ArchStdEvent": "BUS_ACCESS_RD", + }, + { + "ArchStdEvent": "BUS_ACCESS_WR", + } +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index f03e26ec..59cd8604 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -16,3 +16,4 @@ 0x00000000420f5160,v1,cavium/thunderx2,core 0x00000000430f0af0,v1,cavium/thunderx2,core 0x00000000480fd010,v1,hisilicon/hip08,core +0x00000000500f0000,v1,ampere/emag,core -- 2.11.0
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