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openSUSE:Leap:15.4:ARM
qemu-linux-user.26284
0186-pci-host-designware-add-pcie-msi-re.patch
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File 0186-pci-host-designware-add-pcie-msi-re.patch of Package qemu-linux-user.26284
From: Prasad J Pandit <pjp@fedoraproject.org> Date: Tue, 11 Aug 2020 17:11:26 +0530 Subject: pci-host: designware: add pcie-msi read method Git-commit: 4f2a5202a05fc1612954804a2482f07bff105ea2 References: bsc#1173612, CVE-2020-15469 Add pcie-msi mmio read method to avoid NULL pointer dereference issue. Reported-by: Lei Sun <slei.casper@gmail.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org> Message-Id: <20200811114133.672647-3-ppandit@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Bruce Rogers <brogers@suse.com> --- hw/pci-host/designware.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 29ea3137980d28d284f01129ef00..fb0bebc1d690bf0f98b93c3fc2e5 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" +#include "qemu/log.h" #include "hw/pci/msi.h" #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_host.h" @@ -57,6 +58,23 @@ designware_pcie_root_to_host(DesignwarePCIERoot *root) return DESIGNWARE_PCIE_HOST(bus->parent); } +static uint64_t designware_pcie_root_msi_read(void *opaque, hwaddr addr, + unsigned size) +{ + /* + * Attempts to read from the MSI address are undefined in + * the PCI specifications. For this hardware, the datasheet + * specifies that a read from the magic address is simply not + * intercepted by the MSI controller, and will go out to the + * AHB/AXI bus like any other PCI-device-initiated DMA read. + * This is not trivial to implement in QEMU, so since + * well-behaved guests won't ever ask a PCI device to DMA from + * this address we just log the missing functionality. + */ + qemu_log_mask(LOG_UNIMP, "%s not implemented\n", __func__); + return 0; +} + static void designware_pcie_root_msi_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) { @@ -71,6 +89,7 @@ static void designware_pcie_root_msi_write(void *opaque, hwaddr addr, } static const MemoryRegionOps designware_pci_host_msi_ops = { + .read = designware_pcie_root_msi_read, .write = designware_pcie_root_msi_write, .endianness = DEVICE_LITTLE_ENDIAN, .valid = {
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