Sign Up
Log In
Log In
or
Sign Up
Places
All Projects
Status Monitor
Collapse sidebar
openSUSE:Leap:15.4:Update
xen
61e98e89-x86-MSR-split-SPEC_CTRL-handling.patch
Overview
Repositories
Revisions
Requests
Users
Attributes
Meta
File 61e98e89-x86-MSR-split-SPEC_CTRL-handling.patch of Package xen
# Commit 6536688439dbca1d08fd6db5be29c39e3917fb2f # Date 2022-01-20 16:32:11 +0000 # Author Andrew Cooper <andrew.cooper3@citrix.com> # Committer Andrew Cooper <andrew.cooper3@citrix.com> x86/msr: Split MSR_SPEC_CTRL handling In order to fix a VT-x bug, and support MSR_SPEC_CTRL on AMD, move MSR_SPEC_CTRL handling into the new {pv,hvm}_{get,set}_reg() infrastructure. Duplicate the msrs->spec_ctrl.raw accesses in the PV and VT-x paths for now. The SVM path is currently unreachable because of the CPUID policy. No functional change. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com> --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2410,6 +2410,9 @@ static uint64_t vmx_get_reg(struct vcpu switch ( reg ) { + case MSR_SPEC_CTRL: + return v->arch.msrs->spec_ctrl.raw; + default: printk(XENLOG_G_ERR "%s(%pv, 0x%08x) Bad register\n", __func__, v, reg); @@ -2424,6 +2427,10 @@ static void vmx_set_reg(struct vcpu *v, switch ( reg ) { + case MSR_SPEC_CTRL: + v->arch.msrs->spec_ctrl.raw = val; + break; + default: printk(XENLOG_G_ERR "%s(%pv, 0x%08x, 0x%016"PRIx64") Bad register\n", __func__, v, reg, val); --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -28,6 +28,7 @@ #include <asm/hvm/nestedhvm.h> #include <asm/hvm/viridian.h> #include <asm/msr.h> +#include <asm/pv/domain.h> #include <asm/setup.h> #include <public/hvm/params.h> @@ -265,8 +266,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t case MSR_SPEC_CTRL: if ( !cp->feat.ibrsb ) goto gp_fault; - *val = msrs->spec_ctrl.raw; - break; + goto get_reg; case MSR_INTEL_PLATFORM_INFO: *val = mp->platform_info.raw; @@ -424,6 +424,13 @@ int guest_rdmsr(struct vcpu *v, uint32_t return ret; + get_reg: /* Delegate register access to per-vm-type logic. */ + if ( is_pv_domain(d) ) + *val = pv_get_reg(v, msr); + else + *val = hvm_get_reg(v, msr); + return X86EMUL_OKAY; + gp_fault: return X86EMUL_EXCEPTION; } @@ -513,9 +520,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t if ( val & rsvd ) goto gp_fault; /* Rsvd bit set? */ - - msrs->spec_ctrl.raw = val; - break; + goto set_reg; case MSR_PRED_CMD: if ( !cp->feat.ibrsb && !cp->extd.ibpb ) @@ -663,6 +668,13 @@ int guest_wrmsr(struct vcpu *v, uint32_t return ret; + set_reg: /* Delegate register access to per-vm-type logic. */ + if ( is_pv_domain(d) ) + pv_set_reg(v, msr, val); + else + hvm_set_reg(v, msr, val); + return X86EMUL_OKAY; + gp_fault: return X86EMUL_EXCEPTION; } --- a/xen/arch/x86/pv/emulate.c +++ b/xen/arch/x86/pv/emulate.c @@ -92,12 +92,16 @@ void pv_emul_instruction_done(struct cpu uint64_t pv_get_reg(struct vcpu *v, unsigned int reg) { + const struct vcpu_msrs *msrs = v->arch.msrs; struct domain *d = v->domain; ASSERT(v == current || !vcpu_runnable(v)); switch ( reg ) { + case MSR_SPEC_CTRL: + return msrs->spec_ctrl.raw; + default: printk(XENLOG_G_ERR "%s(%pv, 0x%08x) Bad register\n", __func__, v, reg); @@ -108,12 +112,17 @@ uint64_t pv_get_reg(struct vcpu *v, unsi void pv_set_reg(struct vcpu *v, unsigned int reg, uint64_t val) { + struct vcpu_msrs *msrs = v->arch.msrs; struct domain *d = v->domain; ASSERT(v == current || !vcpu_runnable(v)); switch ( reg ) { + case MSR_SPEC_CTRL: + msrs->spec_ctrl.raw = val; + break; + default: printk(XENLOG_G_ERR "%s(%pv, 0x%08x, 0x%016"PRIx64") Bad register\n", __func__, v, reg, val);
Locations
Projects
Search
Status Monitor
Help
OpenBuildService.org
Documentation
API Documentation
Code of Conduct
Contact
Support
@OBShq
Terms
openSUSE Build Service is sponsored by
The Open Build Service is an
openSUSE project
.
Sign Up
Log In
Places
Places
All Projects
Status Monitor