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openSUSE:Maintenance:9577
qemu-testsuite.openSUSE_Leap_42.3_Update
0065-i386-Add-support-for-SPEC_CTRL-MSR.patch
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File 0065-i386-Add-support-for-SPEC_CTRL-MSR.patch of Package qemu-testsuite.openSUSE_Leap_42.3_Update
From 80120c16e21962411b32cfde4ba706f170d33ec6 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini <pbonzini@redhat.com> Date: Tue, 9 Jan 2018 13:45:14 -0200 Subject: [PATCH] i386: Add support for SPEC_CTRL MSR Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20180109154519.25634-3-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> (cherry picked from commit a33a2cfe2f771b360b3422f6cdf566a560860bfc) [BR: BSC#1068032 CVE-2017-5715] Signed-off-by: Bruce Rogers <brogers@suse.com> --- target/i386/cpu.h | 3 +++ target/i386/kvm.c | 15 +++++++++++++++ target/i386/machine.c | 20 ++++++++++++++++++++ 3 files changed, 38 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index a458c3af9b..29019f227b 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -333,6 +333,7 @@ #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) #define MSR_IA32_FEATURE_CONTROL 0x0000003a #define MSR_TSC_ADJUST 0x0000003b +#define MSR_IA32_SPEC_CTRL 0x48 #define MSR_IA32_TSCDEADLINE 0x6e0 #define FEATURE_CONTROL_LOCKED (1<<0) @@ -1080,6 +1081,8 @@ typedef struct CPUX86State { uint32_t pkru; + uint64_t spec_ctrl; + /* End of state preserved by INIT (dummy marker). */ struct {} end_init_save; diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 55865dbee0..9f83c79338 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -89,6 +89,7 @@ static bool has_msr_hv_runtime; static bool has_msr_hv_synic; static bool has_msr_hv_stimer; static bool has_msr_xss; +static bool has_msr_spec_ctrl; static bool has_msr_architectural_pmu; static uint32_t num_architectural_pmu_counters; @@ -1140,6 +1141,10 @@ static int kvm_get_supported_msrs(KVMState *s) has_msr_hv_stimer = true; continue; } + if (kvm_msr_list->indices[i] == MSR_IA32_SPEC_CTRL) { + has_msr_spec_ctrl = true; + continue; + } } } @@ -1667,6 +1672,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level) if (has_msr_xss) { kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss); } + if (has_msr_spec_ctrl) { + kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl); + } #ifdef TARGET_X86_64 if (lm_capable_kernel) { kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar); @@ -1675,6 +1683,7 @@ static int kvm_put_msrs(X86CPU *cpu, int level) kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar); } #endif + /* * The following MSRs have side effects on the guest or are too heavy * for normal writeback. Limit them to reset or full state updates. @@ -2081,6 +2090,9 @@ static int kvm_get_msrs(X86CPU *cpu) if (has_msr_xss) { kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0); } + if (has_msr_spec_ctrl) { + kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0); + } if (!env->tsc_valid) { @@ -2430,6 +2442,9 @@ static int kvm_get_msrs(X86CPU *cpu) env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data; } break; + case MSR_IA32_SPEC_CTRL: + env->spec_ctrl = msrs[i].data; + break; } } diff --git a/target/i386/machine.c b/target/i386/machine.c index 78ae2f986b..8c0d5437fa 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -927,6 +927,25 @@ static const VMStateDescription vmstate_mcg_ext_ctl = { } }; +static bool spec_ctrl_needed(void *opaque) +{ + X86CPU *cpu = opaque; + CPUX86State *env = &cpu->env; + + return env->spec_ctrl != 0; +} + +static const VMStateDescription vmstate_spec_ctrl = { + .name = "cpu/spec_ctrl", + .version_id = 1, + .minimum_version_id = 1, + .needed = spec_ctrl_needed, + .fields = (VMStateField[]){ + VMSTATE_UINT64(env.spec_ctrl, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + VMStateDescription vmstate_x86_cpu = { .name = "cpu", .version_id = 12, @@ -1053,6 +1072,7 @@ VMStateDescription vmstate_x86_cpu = { #ifdef TARGET_X86_64 &vmstate_pkru, #endif + &vmstate_spec_ctrl, &vmstate_mcg_ext_ctl, NULL }
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