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openSUSE:Slowroll:Base:1
mozjs78
Add-riscv64-support.patch
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File Add-riscv64-support.patch of Package mozjs78
From: William Grant <wgrant@ubuntu.com> Date: Tue, 14 Apr 2020 02:18:28 +0200 Subject: Add riscv64 support Bug-Debian: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=932893 Bug-Mozilla: https://bugzilla.mozilla.org/show_bug.cgi?id=1661027 --- build/moz.configure/init.configure | 3 +++ js/src/jit/AtomicOperations.h | 3 ++- js/src/jit/shared/AtomicOperations-feeling-lucky-gcc.h | 5 +++++ mfbt/tests/TestPoisonArea.cpp | 3 +++ python/mozbuild/mozbuild/configure/constants.py | 2 ++ third_party/rust/cc/.cargo-checksum.json | 2 +- third_party/rust/cc/src/lib.rs | 14 +++++++++----- 7 files changed, 25 insertions(+), 7 deletions(-) diff --git a/build/moz.configure/init.configure b/build/moz.configure/init.configure index 5e07418..0c81996 100644 --- a/build/moz.configure/init.configure +++ b/build/moz.configure/init.configure @@ -744,6 +744,9 @@ def split_triplet(triplet, allow_msvc=False): elif cpu == 'sh4': canonical_cpu = 'sh4' endianness = 'little' + elif cpu.startswith('riscv64'): + canonical_cpu = 'riscv64' + endianness = 'little' else: raise ValueError('Unknown CPU type: %s' % cpu) diff --git a/js/src/jit/AtomicOperations.h b/js/src/jit/AtomicOperations.h index 0486cba..d00e276 100644 --- a/js/src/jit/AtomicOperations.h +++ b/js/src/jit/AtomicOperations.h @@ -391,7 +391,8 @@ inline bool AtomicOperations::isLockfreeJS(int32_t size) { #elif defined(__ppc__) || defined(__PPC__) || defined(__sparc__) || \ defined(__ppc64__) || defined(__PPC64__) || defined(__ppc64le__) || \ defined(__PPC64LE__) || defined(__alpha__) || defined(__hppa__) || \ - defined(__sh__) || defined(__s390__) || defined(__s390x__) + defined(__sh__) || defined(__s390__) || defined(__s390x__) || \ + defined(__riscv) # include "jit/shared/AtomicOperations-feeling-lucky.h" #else # error "No AtomicOperations support provided for this platform" diff --git a/js/src/jit/shared/AtomicOperations-feeling-lucky-gcc.h b/js/src/jit/shared/AtomicOperations-feeling-lucky-gcc.h index f002cd4..413591a 100644 --- a/js/src/jit/shared/AtomicOperations-feeling-lucky-gcc.h +++ b/js/src/jit/shared/AtomicOperations-feeling-lucky-gcc.h @@ -70,6 +70,11 @@ # endif #endif +#if defined(__riscv) && __riscv_xlen == 64 +# define HAS_64BIT_ATOMICS +# define HAS_64BIT_LOCKFREE +#endif + #ifdef JS_CODEGEN_NONE # ifdef JS_64BIT # define HAS_64BIT_ATOMICS diff --git a/mfbt/tests/TestPoisonArea.cpp b/mfbt/tests/TestPoisonArea.cpp index fbd3364..0a67e8c 100644 --- a/mfbt/tests/TestPoisonArea.cpp +++ b/mfbt/tests/TestPoisonArea.cpp @@ -169,6 +169,9 @@ static const ia64_instr _return_instr = { # define RETURN_INSTR _return_instr # define RETURN_INSTR_TYPE ia64_instr +#elif defined(__riscv) +#define RETURN_INSTR 0x80828082 /* ret; ret */ + #else # error "Need return instruction for this architecture" #endif diff --git a/python/mozbuild/mozbuild/configure/constants.py b/python/mozbuild/mozbuild/configure/constants.py index 7542dcd..c9dd1bb 100644 --- a/python/mozbuild/mozbuild/configure/constants.py +++ b/python/mozbuild/mozbuild/configure/constants.py @@ -49,6 +49,7 @@ CPU_bitness = { 'mips64': 64, 'ppc': 32, 'ppc64': 64, + 'riscv64': 64, 's390': 32, 's390x': 64, 'sh4': 32, @@ -88,6 +89,7 @@ CPU_preprocessor_checks = OrderedDict(( ('mips64', '__mips64'), ('mips32', '__mips__'), ('sh4', '__sh__'), + ('riscv64', '__riscv && __riscv_xlen == 64'), )) assert sorted(CPU_preprocessor_checks.keys()) == sorted(CPU.POSSIBLE_VALUES) diff --git a/third_party/rust/cc/.cargo-checksum.json b/third_party/rust/cc/.cargo-checksum.json index 417fde7..9836fc6 100644 --- a/third_party/rust/cc/.cargo-checksum.json +++ b/third_party/rust/cc/.cargo-checksum.json @@ -1 +1 @@ -{"files":{"Cargo.lock":"3aff5f8b0a7f4d72852b11b0526f0002e6bf55f19f1ebd6470d7f97fbd540e60","Cargo.toml":"6ab10d9b6a9c6f0909074e6698c90c6b6a7223661ec2e83174d2593117cbe7f2","LICENSE-APACHE":"a60eea817514531668d7e00765731449fe14d059d3249e0bc93b36de45f759f2","LICENSE-MIT":"378f5840b258e2779c39418f3f2d7b2ba96f1c7917dd6be0713f88305dbda397","README.md":"7184fbdf375a057e673257348f6d7584c0dd11b66318d98f3647f69eb610b097","src/bin/gcc-shim.rs":"b77907875029494b6288841c3aed2e4939ed40708c7f597fca5c9e2570490ca6","src/com.rs":"bcdaf1c28b71e6ef889c6b08d1ce9d7c0761344a677f523bc4c3cd297957f804","src/lib.rs":"4753929dbb7b676c19d7cfa06d0a47e37003554b80c536cbf2b892d591ef61c2","src/registry.rs":"3cc1b5a50879fa751572878ae1d0afbfc960c11665258492754b2c8bccb0ff5d","src/setup_config.rs":"7014103587d3382eac599cb76f016e2609b8140970861b2237982d1db24af265","src/winapi.rs":"ea8b7edbb9ff87957254f465c2334e714c5d6b3b19a8d757c48ea7ca0881c50c","src/windows_registry.rs":"388e79dcf3e84078ae0b086c6cdee9cf9eb7e3ffafdcbf3e2df26163661f5856","tests/cc_env.rs":"e02b3b0824ad039b47e4462c5ef6dbe6c824c28e7953af94a0f28f7b5158042e","tests/cflags.rs":"57f06eb5ce1557e5b4a032d0c4673e18fbe6f8d26c1deb153126e368b96b41b3","tests/cxxflags.rs":"c2c6c6d8a0d7146616fa1caed26876ee7bc9fcfffd525eb4743593cade5f3371","tests/support/mod.rs":"71620b178583b6e6e5e0d4cac14e2cef6afc62fb6841e0c72ed1784543abf8ac","tests/test.rs":"1605640c9b94a77f48fc92e1dc0485bdf1960da5626e2e00279e4703691656bc"},"package":"aa87058dce70a3ff5621797f1506cb837edd02ac4c0ae642b4542dce802908b8"} \ No newline at end of file +{"files":{"Cargo.lock":"3aff5f8b0a7f4d72852b11b0526f0002e6bf55f19f1ebd6470d7f97fbd540e60","Cargo.toml":"6ab10d9b6a9c6f0909074e6698c90c6b6a7223661ec2e83174d2593117cbe7f2","LICENSE-APACHE":"a60eea817514531668d7e00765731449fe14d059d3249e0bc93b36de45f759f2","LICENSE-MIT":"378f5840b258e2779c39418f3f2d7b2ba96f1c7917dd6be0713f88305dbda397","README.md":"7184fbdf375a057e673257348f6d7584c0dd11b66318d98f3647f69eb610b097","src/bin/gcc-shim.rs":"b77907875029494b6288841c3aed2e4939ed40708c7f597fca5c9e2570490ca6","src/com.rs":"bcdaf1c28b71e6ef889c6b08d1ce9d7c0761344a677f523bc4c3cd297957f804","src/lib.rs":"bbdfbab457b93c1f3fa58b97c99974a8cd61de38a9ea0a618ca73b0fb55c4d74","src/registry.rs":"3cc1b5a50879fa751572878ae1d0afbfc960c11665258492754b2c8bccb0ff5d","src/setup_config.rs":"7014103587d3382eac599cb76f016e2609b8140970861b2237982d1db24af265","src/winapi.rs":"ea8b7edbb9ff87957254f465c2334e714c5d6b3b19a8d757c48ea7ca0881c50c","src/windows_registry.rs":"388e79dcf3e84078ae0b086c6cdee9cf9eb7e3ffafdcbf3e2df26163661f5856","tests/cc_env.rs":"e02b3b0824ad039b47e4462c5ef6dbe6c824c28e7953af94a0f28f7b5158042e","tests/cflags.rs":"57f06eb5ce1557e5b4a032d0c4673e18fbe6f8d26c1deb153126e368b96b41b3","tests/cxxflags.rs":"c2c6c6d8a0d7146616fa1caed26876ee7bc9fcfffd525eb4743593cade5f3371","tests/support/mod.rs":"71620b178583b6e6e5e0d4cac14e2cef6afc62fb6841e0c72ed1784543abf8ac","tests/test.rs":"1605640c9b94a77f48fc92e1dc0485bdf1960da5626e2e00279e4703691656bc"},"package":"aa87058dce70a3ff5621797f1506cb837edd02ac4c0ae642b4542dce802908b8"} diff --git a/third_party/rust/cc/src/lib.rs b/third_party/rust/cc/src/lib.rs index 621d31d..968d03a 100644 --- a/third_party/rust/cc/src/lib.rs +++ b/third_party/rust/cc/src/lib.rs @@ -1365,10 +1365,10 @@ impl Build { cmd.push_cc_arg("-ffunction-sections".into()); cmd.push_cc_arg("-fdata-sections".into()); } - // Disable generation of PIC on RISC-V for now: rust-lld doesn't support this yet + // Disable generation of PIC on bare-metal for now: rust-lld doesn't support this yet if self .pic - .unwrap_or(!target.contains("windows-gnu") && !target.contains("riscv")) + .unwrap_or(!target.contains("windows") && !target.contains("-none-")) { cmd.push_cc_arg("-fPIC".into()); // PLT only applies if code is compiled with PIC support, @@ -1588,13 +1588,16 @@ impl Build { if let Some(arch) = parts.next() { let arch = &arch[5..]; cmd.args.push(("-march=rv".to_owned() + arch).into()); - // ABI is always soft-float right now, update this when this is no longer the - // case: - if arch.starts_with("64") { + if target.contains("linux") && arch.starts_with("64") { + cmd.args.push("-mabi=lp64d".into()); + } else if target.contains("linux") && arch.starts_with("32") { + cmd.args.push("-mabi=ilp32d".into()); + } else if arch.starts_with("64") { cmd.args.push("-mabi=lp64".into()); } else { cmd.args.push("-mabi=ilp32".into()); } + cmd.args.push("-mcmodel=medany".into()); } } } @@ -2024,6 +2027,7 @@ impl Build { "riscv32imac-unknown-none-elf" => Some("riscv32-unknown-elf"), "riscv32imc-unknown-none-elf" => Some("riscv32-unknown-elf"), "riscv64gc-unknown-none-elf" => Some("riscv64-unknown-elf"), + "riscv64gc-unknown-linux-gnu" => Some("riscv64-linux-gnu"), "riscv64imac-unknown-none-elf" => Some("riscv64-unknown-elf"), "s390x-unknown-linux-gnu" => Some("s390x-linux-gnu"), "sparc-unknown-linux-gnu" => Some("sparc-linux-gnu"),
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