- update to 2.1 (boo#1119656):
  + updated interface
  + Support for textual Verilog module definitions.
  + All gates are now rotatable. Use Tab/Backtab to rotate selection.
  + Automatic interface generator.
  + Support for user defined symbols.
  + Hierarchical module browser.
  + Jump-to-module supported while in simulation mode.
  + Expanded and dockable toolbars.
  + Better library support.
  + Pinout options on concat, muxes, and demuxes.
  + Implement import/export of X bitmaps in symbol editor
  + Grab and scroll tool (and auto grab with button 2)
  + New options setting dialog box
  + Mouse over highlighting for tabs
  + Wires with bit sizes greater than 32 bits
  + Fixed bug with warning reporting in simulation mode
  + Updated print dialog box
  + Updated library manager and added it to the circuit properies box
  + Localization updates
  + Partial fix for whitespace in filenames
  + Add manuals about circuits 74xx for all languages
  + Gettext support for messages, examples, tutorials
  + any many, many bug fixes
- removed patches:
  + tkgate-config.h.patch
  + tkgate-elistbox.patch
  + tkgate-honour-localdir.patch
  + tkgate-incorrect-fsf-address.diff
  + tkgate-manpages.patch

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part 1 of the fix to get it built on newer TCL versions

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- fix license to be in SPDX format
- specfile cleanup

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- use libdir instead of libexecdir

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fix install

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fix build

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