verilator
Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.
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osc -A https://api.opensuse.org checkout home:dirkmueller:Factory/verilator && cd $_
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Source Files (show unmerged sources)
Filename | Size | Changed |
---|---|---|
verilator-4.228.tar.gz | 0002623600 2.5 MB | |
verilator.changes | 0000008054 7.87 KB | |
verilator.spec | 0000003260 3.18 KB |
Latest Revision
buildservice-autocommit
accepted
request 1032204
from
Dirk Mueller (dirkmueller)
(revision 3)
baserev update by copy to link target
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