verilator
Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog and test-bench code, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.
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osc -A https://api.opensuse.org checkout home:ila.embsys:branches:electronics/verilator && cd $_
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Source Files (show unmerged sources)
Filename | Size | Changed |
---|---|---|
_service | 0000000701 701 Bytes | |
_service:obs_scm:verilator.obscpio | 0043223565 41.2 MB | |
_service:obs_scm:verilator.obsinfo | 0000000098 98 Bytes | |
_service:set_version:verilator.spec | 0000003425 3.34 KB | |
verilator.changes | 0000013318 13 KB | |
verilator.spec | 0000003425 3.34 KB |
Latest Revision
Ilya Stolyarov (ila.embsys)
committed
(revision 4)
- Add service
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